Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes

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Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can obtain significant coding gain over the hard-decision decoding (HDD). Compared with other ASD algorithms, the low-complexity Chase (LCC) decoding algorithm needs less computation complexity with similar or higher coding gain. Besides employing complicated interpolation algorithm, the LCC decoding can also be implemented based on the HDD. However, the previous syndrome computation for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors and the key equation solver (KES) in the HDD requires long latency and remarkable hardware. In this brief, a unified syndrome computation algorithm and the corresponding architecture are proposed. Cooperating with the KES in the reduced inversion-free Berlekamp-Messy algorithm, the reduced-complexity LCC RS decoder can speed up by 57% and the area will be reduced to 62% compared with the original design for η = 3.

A novel scheme is presented for encoding and decoding of Reed-Solomon codes of prime lengths. Encoding is performed on a collection of codewords which are mapped through Galois Fourier transform into a codeword in a low-density parity-check code with a binary parity-check matrix for transmission. Using this matrix, a binary iterative soft-decision decoding algorithm is applied to jointly decode a collection of codewords in the Reed-Solomon code. By allowing information sharing among the received vectors corresponding to the code-words in the collection, the proposed decoding scheme achieves superior performance over algorithms decoding individual Reed-Solomon codewords including maximum likelihood decoding.

A novel iterative approach for soft-decision decoding of Reed-Solomon codes is presented that employs symbol-level belief propagation on an alternative parity-check matrix representation of the code. Construction of a suitable matrix is discussed from the viewpoint of iterative decoding, and certain conditions are derived on existence of structures detrimental for decoding. Simulation results demonstrate that the novel scheme performs substantially better than hard-decision decoding, especially with high rate codes, while being of much lower complexity than existing soft-decision decoding methods. Proposed method is also well-suited for efficient hardware implementations.

This paper presents an FPGA implementation of a high-speed interpolation processor for algebraic soft-decision decoding of Reed-Solomon codes. In the design, pipelining and parallel processing techniques are exploited to increase the decoding throughput. In addition, different parts of the interpolation processor are properly scheduled to achieve maximum overlap in processing time for the computations occurring at adjacent iterations. Synthesis results show that the FPGA implementation of the interpolation architecture can achieve a throughput of 149Mbps, which is multiple times higher than conventional design.

Reed-Solomon (RS) codes are used as error-correcting codes in numerous digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the iterative bit-level generalized minimum distance (BGMD) decoding can achieve similar or higher coding gain with lower complexity. The interpolation is a major step of ASD. The maximum achievable speed of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, a novel interpolation scheme that is capable of combining multiple interpolation iterations, as well as sharing interpolation results from previous decoding iterations, is developed for the iterative BGMD decoding. In addition, efficient VLSI architectures are proposed to implement the developed scheme. Based on the proposed architectures, an interpolator for a (255, 239) RS code is implemented on field programmable gate array (FPGA) devices. On a Xilinx Virtex-II device, our interpolator can achieve a throughput of 440 Mbps, which is 64% higher than the fastest previous design, with 51% less FPGA resource.

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. To reduce the complexity of ASD decoders, reencoding and coordinate transformation need to be applied, which require a reencoder and an erasure decoder. In the reencoded and transformed ASD decoders, these two blocks take a significant part of the overall decoder area and may limit the achievable throughput. In this brief, the reencoder design based on direct polynomial multiplication is further simplified by reformulating the involved equations. Moreover, two innovative area-reducing methods are proposed for the transformed coordinate computation. Efficient architectures are developed for the proposed schemes, and two reencoders are implemented using 0.18- CMOS technology. For a (255, 239) RS code, both reencoders can achieve throughput of at least 1.77 Gb/s and more than 30% higher efficiency in terms of throughput-over-area ratio than prior work. With minor modifications, the proposed design can also be employed to implement efficient erasure decoding.

Reed-Solomon (RS) codes are error-correcting codes used in many of today's communication systems. RS encoding and decoding are typically implemented using dedicated hardware elements used in ADSL modems and digital TV. In this paper we propose using software in lieu of a hardware-based RS de-coder. This is accomplished using the Berlekamp-Massey algorithm, implemented on a programmable DSP. This software-based RS decoder using Berlekamp-Massey is implemented on Motorola's MSC8101 StarCore DSP. In order to evaluate the algorithm we use the following criteria: computation cost; cycle count, critical paths in the decoding scheme, and error location in the codeword. Furthermore, we examine the effect of changing the RS code's k, t parameters and its primitive polynomial in real-time implementation. The Berlekamp-Massey algorithm operates over finite field arithmetic, whose steps, as applied on the StarCore DSP, are discussed in detail and specifically evaluated using the assembly code for the syndrome search. We conclude that the Berlekamp-Massey algorithm, used for RS decoding, should be implemented using long codewords.

Non-binary multithreshold decoding (qMTD) for q-ary self-orthogonal codes (qSOC) is considered. The SER performance of qMTD is shown to be close to the results provided by optimum total search methods, which are not realizable for non-binary codes in general. qMTD decoders are compared with different decoders for Reed-Solomon codes. The performance provided with qMTD in some cases is unattainable with classical decoders for arbitrary long Reed-Solomon codes. The result of concatenation of qSOC with simple to decode outer codes is described. Method of improving of qMTD decoder's performance for qSOC is offered. Some simulated results obtained by using these two decoding techniques (the base and modified ways) are presented as well. Comparison of the results showed that the change in the threshold element's algorithm can significantly improve speed of qMTD work. It's shown that for a larger gain this modification qMTD should be used after conventional decoding iterations.

This paper presents a high-throughput variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS (255,239) code but also various shortened RS codes. Moreover, the variable-length architecture provides low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-nm CMOS standard cell technology, the proposed variable-length RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-Gbps data rate at clock frequency 300 MHz.

Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.

A new iterative soft decision decoding method for Reed-Solomon (RS) codes is proposed. This method is based on bit level belief propagation (BP) decoding. In order to make BP decoding effective for RS codes, we use an extended binary parity check matrix with a lower density and reduced number of 4-cycles compared to the original binary parity check matrix of the code. In our proposed method, we take advantage of the cyclic structure of RS codes. Based on this property, we can apply the belief propagation algorithm on any cyclically shifted version of the received symbols with the same binary parity check matrix. For each shifted version of received symbols, the geometry of the factor graph will change and deterministic errors can be avoided. Our method results in considerable performance improvement of RS codes compared to hard decision decoding. The performance is also superior to some popular soft decision decoding methods.

In this chapter, we will give information about Reed-Solomon codes. These codes fall into the category of nonbinary cyclic codes. The generator polynomials of Reed-Solomon codes are constructed using the minimal polynomials of the extended finite fields. Reed-Solomon codes are effective for burst errors and they are used for erasure decoding. Reed-Solomon codes are used in some electronic devices such as CDs, DVDs, and Blu-ray, and they are also employed in communication technologies such as DSL, WiMAX, or RAID 6. Reed-Solomon codes are invented in 1960, and they are seen as nonbinary BCH codes. In this chapter, we first explain the construction of the generator polynomials of the Reed-Solomon codes using the minimal polynomials of the extended finite fields. Next, we provide information about the syndrome decoding of Reed-Solomon codes using error evaluator polynomial. In sequel, Berlekamp algorithm which is a low-complexity syndrome decoding algorithm used for the decoding of Reed-Solomon codes is explained.

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.