Efficient searching with parallel TCAM chips

Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM. Due to the fact that not all rules can be distinguished using one field, our scheme employs a TCAM-based multimatch packet classification technique to ensure correctness. We further develop approaches to reduce redundant TCAM accesses for multimatch packet classification. Although our scheme requires additional TCAM accesses, it supports packet classification upon long rules with narrow TCAM entries, and drastically reduces the required TCAM storage. Our experimental results show that our scheme requires a moderate number of additional TCAM accesses and consumes much less storage compared to the basic TCAM-based packet classification. Thus, it can provide the required scalability for long rules required by potential applications of SDN.

Ternary content addressable memory (TCAM) is a key component in various digital systems due to its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. One march-like test algorithm TAC-H is also proposed to cover the defined comparison faults. The TAC-H consists of 8N Write operations and (3N + 2B) Compare operations for an N × B-bit TCAM with Hit output only. We also propose two march-like diagnosis algorithms to identify the defined comparison faults of TCAMs with asymmetric cells. The first diagnosis algorithm DAC-H requires 5N Write operations, 3N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit output only. The second diagnosis algorithm DAC-P requires 3N Write operations, 1N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit and priority address encoder outputs.

An efficient IP address lookup algorithm based on a small balanced tree using entry reduction

IP 주소 검색은 라우터에서 가장 중요하고 복잡한 기능중 하나이다. 본 논문에서는 고성능 라우터에서 IP 주소 검색의 성능을 향상시키기 위해 LC-trie를 개선하는 기법을 제안한다. TCAM(Ternary Content Addressable Memory)에서 테이블 압축을 위해 이용한 프리픽스 pruning 방법을 LC-trie에 효과적으로 적용한다. 이러한 기법은 메모리 참조 횟수를 감소시키고 검색의 속도를 높일 수 있다. 또한, 실제 사용되는 포워딩 테이블과 트래픽 분포를 사용하여 검색 시간과 메모리 참조 횟수 둥의 관점에서 개선된 기법의 성능을 기존의 LC-trie 기법과 비교 평가한다. IP address lookup is one of the most important and complex functions in the router. In this paper, we propose an improved technique of LC-trie to increase the performance of IP address lookup in the high performance router. We effectively apply the prefix pruning method, which is used for the compression of the forwarding table in TCAM((Ternary Content Addressable Memory), to the LC-trie. This technique can decrease the number of memory accesses and upgrade the lookup speed. Moreover, through the real forwarding table and the real traffic distribution, we evaluate the performance of our scheme in terms of the lookup time and the number of memory access, comparing with that of the previous LC-trie.

As data rates in the Internet increase, the Internet Protocol (IP) address lookup is required to be resolved in shorter resolution times. IP address lookup involves finding the longest matching prefix from a database of prefixes that better matches the destination address of a packet. The fastest IP-address lookup solutions are based on ternary content addressable memories (TCAMs), which can resolve the IP lookup in one memory-access time. However, TCAMs have a high power consumption and large complexity that may limit their scalability and storage capacity. An alternative is to use random access memory (RAM) that stores a forwarding table in a trie form. Proposed trie-based solutions for IP lookup require three or more memory-access times in the worst-case scenario. This makes them unattractive despite their reduced power consumption. In this paper, we propose a flexible and fast trie-based IP-lookup algorithm where parallel searching is performed. This algorithm performs lookup in two memory- access times whith a feasible amount of memory or three memory access times with reduced memory.

A power-saving pre-classifier for TCAM-based IP lookup

Ternary content addressable memories (TCAMs) are becoming very popular due to the simple-to-design IP lookup units included in high-speed routers; they are fast and simple to manage, and they provide a one-clock lookup solution. However, a major drawback of TCAM-based IP lookup schemes lies in their high power consumption. Thus, the rapid increase of routing tables inevitably deteriorates TCAM power efficiency. Although on-chip TCAM minimizers aim for the TCAM power efficiency in a fast time and at a small memory amount, the minimizers are not efficient in a large scale prefix table. In this paper, we present a hash-based on-chip TCAM minimization for a power-and throughput-efficient IP lookup. In a hash-based TCAM minimization (HTM), we convert prefixes into keys and merge keys with a fast hash lookup in an O(nW) complexity, where n is the number of prefixes and W is the number of IP bits. Additionally, by building a forest of merging trees and choosing a subset among them, we can achieve a higher minimization ratio. The simulation with two routing tables shows that our HPM scheme uses 8.6 and 4.0 times fewer computation time and memory, compared to a contemporary on-chip minimizer.

Efficient packet classification using TCAMs

This paper discusses the feasibility of the use of minimum independent prefix set (MIPS) algorithm in a ternary content addressable memory (TCAM) based parallel architecture proposed for high speed packet switching. MIPS algorithm is proposed earlier to transform a forwarding table into one that contains the minimum independent prefix set. In this paper we propose MIPS algorithm to be integrated into a TCAM based parallel IP lookup engine. We first analyze the table compression performance of the MIPS algorithm and demonstrate that it may lead to routing table expansion rather than compression in general. For certain cases on the other hand, MIPS algorithm performs well and is suitable to be used in TCAM based parallel IP lookup engine. We demonstrate that with the adoption of the MIPS algorithm, the overall performance, in terms of throughput, of the IP lookup engine can be enhanced considerably.

The IP address lookup in the communication link technologies is becoming a major bottleneck by exploring the exact matching and the parallel hashing in each prefix length. In this paper, we present an algorithm for IP address lookup and collision resolution to reduce memory space and solve collision for high speed routing based on multiple table indexing structure. Our scheme makes possible direct access in a designated IP prefix without replicating the forwarding table entries, and provides efficient collision resolution for fast route lookup with only small memory. Simulation results indicate that our algorithm provides a faster lookup than the conventional lookup schemes.

A fast IPv6 route lookup scheme implemented by hardware is proposed in this paper. It supports a fast IP address lookup and can insert and delete the prefixes effectively. A novel compressed multibit trie algorithm that decreases the memory space occupied and the average searching time is applied. The scheme proposed in this paper is superior to other IPV6 route lookup ones, for example, by using SRAM pipeline, a lookup speed of 125 x 10 6 per second can be realized to satisfy 40Gbps optical link rate with only 1.9Mbyte consumption of memory space. As there is no actual IPv6 route prefix, we generate various simulation databases in which prefix length distribution is different. Simulation results show that our scheme has reasonable lookup time, memory space for all the prefix length distribution.

Because of rapid increase in link capacity, an Internet router has to complete routing lookup function in a much shorter amount of time in order to keep up with the line rate. Many fast routing lookup algorithms have been proposed in the past. Because most of them require some memory accesses, their lookup speed is limited by memory access speed. IP address caching has been used to improve upon existing routing lookup algorithms by storing the most recently referenced IP address. Most recently, routing prefix caching has been proposed to increase caching effectiveness. In this paper, we evaluate techniques to further reduce cache miss ratio, thereby, increase caching effectiveness for a routing prefix cache. We first study the effect of routing. table compaction, which reduces the routing table size. Then we propose and evaluate a new cache replacement policy that outperforms both least recently used and least frequently used replacement policy. The experiment result shows that up to 39% percent reduction in cache miss ratio could be achieved. It further proves that routing prefix cache has the potential to greatly outperform IP address cache.

Address lookup is one of the main functions of the Internet routers and a very important feature in evaluating router performance. As the Internet traffic keeps growing and the number of routing table entries is continuously growing, efficient address-lookup mechanism is essential. In recent years, various fast address-lookup schemes have been proposed, but most of those schemes are not practical in terms of the memory size required for routing table and the complexity required in table update. In this paper, we have proposed a parallel IP address lookup architecture based on multiple hashing. The proposed scheme has advantages in required memory size, the number of memory accesses, and table update. We have evaluated the performance of the proposed scheme through simulation using data from MAE-WEST router. The simulation result shows that the proposed scheme requires a single memory access for the address lookup of each route when 203 kbytes of memory and a few-hundred-entry TCAM are used.

The current sharing of the chips in parallel is one of the key points of the layout design of IGBT module. The current imbalance of the chips leads to imbalance losses and temperature, and increases the failure of the chip with highest temperature, so attention should be paid during the IGBT module design. In this paper, the asymmetric stray parameters of the circuit in parallel and the coupling between the gate circuit and the power circuit are analyzed by the equivalent circuit method, but the simulation results and the experimental results show that the stray inductances and resistances, extracted at the fixed frequency, can't reflect the electrical behaviors of the power and gate circuit. A method to extract the stray parameters is proposed in this paper, which can be used to reflect the current imbalance of the switching and conducting behaviors.

IP address lookup algorithms can be evaluated on a number of metrics lookup time, update time, memory usage, and to a lesser extent, the time to construct the data structure used to support lookups and updates. Many of the existing methods are geared towards optimizing a specific metric, and hence do not scale well with the ever expanding routing tables and the forthcoming IPv6 with 128 bit long IP address. In contrast, our effort is directed at simultaneously optimizing multiple metrics and provide solutions that scale well to IPv6. In this paper, we present two IP address lookup schemes Elevator - Stairs algorithm and logW - Elevators algorithm. For a routing table with N prefixes, The Elevator - Stairs algorithm uses optimal O(N) memory, and achieves better lookup and update times than other methods with similar memory requirements. The logW - Elevators algorithm gives O(log W) lookup time, where W is the length of an IP address, while improving upon update time and memory usage. Experimental results using the MAE-West router with 29,487 prefixes show that the Elevator - Stairs algorithm gives an average throughput of 15.7 Million lookups per second (Mlps) using 459 KB of memory, and the logW - Elevators algorithm gives an average throughput of 21.41 Mlps with a memory usage of 1259 KB.