Electrical stability of pentacene thin film transistors

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, by measurements at low revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic The generation of this excellent interface is in virtually hysteresis-free characteristics of all the One important that the performance of OTFTs, and in the charge carrier is the of the As shown by several the of the surface energy of the to that of the is one important the growth For a low surface energy material with a smooth surface TMSC, a growth mode is and with a rather high density and small grain sizes are formed (see Figure The high density of grain a significant decrease of the charge carrier since grain as charge On the a better between pentacene on low surface energy materials TMSC with and better reduce the of trap thus the mobility of charge in the In there is an between grain related and interface with regard to their influence on charge carrier The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which the influence of the large grain trap density on the charge carrier Accordingly, a mobility 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the of the fullerene In the pentacene OTFTs (see Figure a non-linear current increase in the linear regime of the ID(VDS) output characteristics is at higher gate have been in to such a which can be observed in bottom gate The explanations i) the of the charge carrier mobility for semiconductor ii) currents that the of the mobile by an effective under the drain and iii) large at the electrode from an energy between the work of contact material and semiconductor films, a gate or large contact are found in our of these it has been shown that a mobility in combination with a small contact in a non-linear drain voltage dependence of the current due to The from a of from trap and a dependence of on the drain A respective of the pentacene output curve in Figure the dependence in the regime 2 V, thus indicating that a mobility has to be The of any hysteresis in the I(V) curves and the low and value of the subthreshold swing a low density of interface in the pentacene are not for the observed and the of the as by the of the pentacene layer gives rise to which to a field dependence of the charge carrier This is all the more given that the pentacene grain sizes are 300 nm at a large density of grain As by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts storage which after a of measurements. The virtually subthreshold swing in pentacene as well as the negligible hysteresis as the origin of the On the contrary, it seems that trap are for the positive onset voltage shift in are either over time or during the first measurements by the applied positive gate be easily by the gate bias and therefore are not to the swing, but the small onset voltage in pentacene-based It has been reported by many that the of the of trap in pentacene trap also be due to such as at the a at the or a at the fabrication and transfer from the to the measurement stage the semiconductor layer and rise to such For oxygen can even the devices are to but transferred directly and measured in a glovebox with reduced oxygen and water have also observed that the of oxygen with pentacene is in the that these are under device operation with the of oxygen in the grain observed that the storage of devices in and their subsequent measurement in did not a change in their I(V) also observed that the storage time to the first measurement has influence on the device (i.e., on the onset voltage in this of and the first measurement the of to the of oxygen or with the which in a second are by Moreover, also are are not as in the as the (see and This an for the positive shift of the onset voltage between first and second measurement (Figure and also for the saturation of the onset voltage shift in In order to clarify which of are present in our we performed measurements on pentacene films (in and after storage in for (see Figure Supporting Information). storage under a small increase of the at energy is observed that can be attributed to the to and The analysis reveals an increase of the from 0.2 to At the position no change is that trap in our devices for bias stress and the positive onset voltage can mainly be attributed to It be that the of any mobility in pentacene OTFTs against an of pentacene both are to oxygen For the C60 transistors, one a strong decrease of the charge carrier mobility during 8 days of storage which is by all over the device grain This is a effect of The decrease in charge carrier mobility and the at the interface that the subthreshold swing is in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond from the maximum theoretical value for all supply voltages are and the high operational of the OTFT devices. At a very low supply voltage of 4 V, our bilayer organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is already reported devices with architecture (see the of inverter performance given in 38 and also gain values above 1000 V/V values up to 1600 were measured for our devices. This is all the most as the charge carrier mobility values of the transistors are not thus the that the of the mobility values between p- and n-channel with the virtually hysteresis are the factors for high gain and high noise margin Accordingly, a mobility 1 be the the is not high ≤ it can be by and p-channel transistors with different In our the mobility is The static of a complementary inverter is determined by technology parameters, the parameters of p- and n-type transistors. A good of these parameters a good saturation of both output can to a significant increase of the gain A is shown in the Supporting Furthermore, high gain values are also determined by the interface An insulator with an low trap density (as this is the for is in having I(V) curves with virtually zero Accordingly, it is to measurements with a very high voltage small voltage thus one to the high gain value of the complementary inverter it by hysteresis The noise margin with increasing VDD due to their strong this is also for the of the VTCs by see Figure A for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate and the positive

Modeling of bias-induced changes of organic field-effect transistor characteristics

In this study, the environmental dependence of the electrical stability of solution-processed n-channel zinc tin oxide (ZTO) thin-film transistors (TFTs) is reported. Under a prolonged negative gate bias stress, a negative shift in threshold voltage occurs in atmospheric air, whereas a negligible positive shift in threshold voltage occurs under vacuum. In the positive bias-stress experiments, a positive shift in threshold voltage was invariably observed both in atmospheric air and under vacuum. In this study, the negative gate-bias-stress-induced instability in atmospheric air is explained through an internal potential in the ZTO semiconductor, which can be generated owing to the interplay between H2O molecules and majority carrier electrons at the surface of the ZTO film. The positive bias-stress-induced instability is ascribed to electron-trapping phenomenon in and around the TFT channel region, which can be further augmented in the presence of air O2 molecules. These results suggest that the interaction between majority carriers and air molecules will have crucial implications for a reliable operation of solution-processed ZTO TFTs.

Electrical instabilities of a-IGZO TFTs under different conditions of bias and illumination stress

Indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted much attention because of their high electron mobility values (> 10 cm2/Vs) and because they can be processed at low temperature to produce large-area displays with the potential of low production costs. The IGZO TFTs require smaller RC signal delay with shorter channel length for high-resolution display applications. Therefore, it’s necessary to use self-aligned top-gate (TG) oxide TFT structure with smaller channel length for high-resolution, high-speed, low-power, and narrow-bezel displays. The IGZO TFTs also need good electrical stability under positive/negative bias temperature stress (P/NBTS) with decent TFT properties for peripheral gate driver integrated large size organic light emitting diode (OLED) TVs. TG IGZO TFTs for display applications such as OLED TVs typically use longer channel length (> 4 µm) due to negative threshold voltage (Vth) shift and Vth non-uniformity issues with smaller channel length, which is mainly caused by hydrogen diffusion near source/drain regimes during device integration. We fabricated TG IGZO TFTs by using Applied Material’s CVD/PVD tools to achieve excellent electrical stability and Vth uniformity by balancing oxygen and hydrogen diffusion into oxide channel layer such as IGZO. Suppressing carrier densities at the interface between gate insulator (GI) and IGZO by increasing oxygen diffusion with IGZO pre-annealing in air and TFT post anneal in air, and by minimizing vacuum annealing impact during GI deposition makes the IGZO TFTs more resistive with more positive Vth shift. On the other hands, more hydrogen diffusion into IGZO from GI, ILD, and passivation layers during device integration or TFT post annealing makes the IGZO TFTs more conductive with more negative Vth shift and worse Vth uniformity, but it helps to improve electrical stability with smaller Vth shift under PBTS by passivating defects inside IGZO. Therefore, there is trade-off between Vth uniformity and electrical stability due to the dominance of the diffusion between oxygen and hydrogen. By balancing the diffusion of oxygen and hydrogen, the IGZO TFTs can minimize negative Vth shift even with shorter channel for high-resolution display applications and achieve good electrical stability for pixel and peripheral gate driver circuits integrated in display panel. We successfully demonstrated excellent electrical properties such as high mobility (µFE), low sub-threshold slope (SS), good threshold voltage (Vth) position, and low off-leakage current from TG IGZO TFTs. The positions of Vth can be optimized by controlling carrier densities at the interface between GI and IGZO during device integration even with different GI temperature and power (Fig. 1). Here, GI type A is deposited at a low temperature of 225 ºC with a high RF power of 2400 W. GI type B is deposited at a high temperature of 270 ºC with a high RF power of 2400 W. GI type C is deposited at a high temperature of 270 ºC with a low RF power of 1600 W. In order to investigate the channel length dependency of Vth, Vth values were extracted from transfer characteristics at VDS = +1 V with various TFTs by fixing channel width of 12 µm and varying the channel length from 10 µm down to 3 µm. The differences between maximum Vth and minimum Vth, Vth (Max–Min), from GI type A, B, and C are 0.35 V, 0.48 V, and 1.20 V, respectively. Total resistance in TFTs was extracted from the measured IDS values by varying VGS from 12 V to 20 V with channel length from 10 µm down to 5 µm by transmission line method. Extracted 2∆L, the difference between mask channel length and effective channel length, from GI type A, B, and C are 0.78 µm, 0.87 µm, and 1.05 µm, respectively. The IGZO TFTs with higher GI power show better TFT uniformity than lower power GI without notable negative Vth shift and non-uniformity even with shorter channel length from 10 µm down to 3 µm by minimizing hydrogen diffusion into IGZO (Fig. 2). The IGZO TFTs with lower GI power show better stability under PBTS due to more hydrogen diffusion into IGZO. On the other hands, the IGZO TFTs show better stability under both PBTS and NBTS with higher GI temperature than lower temperature GI due to more hydrogen diffusion into IGZO (Fig. 3). Therefore, high power/high temperature GI is preferred for high-resolution mobile/VR displays considering short channel length effect and low power/high temperature GI is preferred for gate driver integrated OLED TVs considering stability, especially PBTS. Figure 1

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

Improved bias stress stability of In–Ga–Zn–O thin film transistors by UV–ozone treatments of channel/dielectric interfaces

In this article, NaxCu1−xI thin-film transistors gated by chitosan for low-voltage operation have been created by doping CuI with different Na concentrations (x = 0, 0.05, 0.1). It is found that the devices exhibit optimal performance when x is 0.05: a large current on/off ratio of 1.62 × 105, a steep subthreshold slope of 17.72 mV/dec, a saturation field-effect mobility of 0.51 cm2/V s, and a threshold voltage of 1.10 V. The operating voltage of the devices is reduced to below 2 V due to the electric-double-layer (EDL) effect. At a frequency of 10 Hz, a maximum specific capacitance of 1.36 μF/cm2 can be obtained in the chitosan. The effects of bias stress and laser on Na0.05Cu0.95I thin-film transistors (TFTs) have been examined at the end of the article, and the results revealed that Na0.05Cu0.95I TFTs possess good stability. As the bias stress gets longer and the laser power increases, the transfer curves of TFTs shift positively. Also, artificial synaptic behaviors and functions have been simulated experimentally. It can be divided into single-pulse, double-pulse, and multiple-pulse. According to the experimental results, features such as short-term plasticity, long-term plasticity, paired-pulse facilitation, high-pass filtering, pulse logic, and spatial summation have been achieved. The electrostatic modulation of EDL due to proton transverse migration is vital for this simulation. The realization of low-voltage synaptic Na0.05Cu0.95I TFTs prepared by solution method with pulse logic and spatial summation functions is crucial for application of portable biosensors and neuromorphic systems.

In this work, a high-resolution microscopic gate-modulation imaging (μ-GMI) technique is successfully developed to visualize inhomogeneous charge and electric field distributions in operating organic thin-film transistors (TFTs). We conduct highly sensitive and diffraction-limit gate-modulation sensing for acquiring difference images of semiconducting channels between at gate-on and gate-off states that are biased at an alternate frequency of 15 Hz. As a result, we observe unexpectedly inhomogeneous distribution of positive and negative local gate-modulation (GM) signals at a probe photon energy of 1.85 eV in polycrystalline pentacene TFTs. Spectroscopic analyses based on a series of μ-GMI at various photon energies reveal that two distinct effects appear, simultaneously, within the polycrystalline pentacene channel layers: Negative GM signals at 1.85 eV originate from the second-derivative-like GM spectrum which is caused by the effect of charge accumulation, whereas positive GM signals originate from the first-derivative-like GM spectrum caused by the effect of leaked gate fields. Comparisons with polycrystalline morphologies indicate that grain centers are predominated by areas with high leaked gate fields due to the low charge density, whereas grain edges are predominantly high-charge-density areas with a certain spatial extension as associated with the concentrated carrier traps. Consequently, it is reasonably understood that larger grains lead to higher device mobility, but with greater inhomogeneity in charge distribution. These findings provide a clue to understand and improve device characteristics of polycrystalline TFTs.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔVTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔVTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

In this study, we report a novel vertical diffusion method for fabricating solution-processed quaternary In-Ga-Zn-O (IGZO) (defined as vd-IGZO) thin-film transistors (TFTs). Compared with conventional IGZO (defined as con-IGZO) TFT annealed at 380°C, vd-IGZO thin film is to spin coat Ga2O3, ZnO and In2O3 binary oxide precursors consecutively and then anneal at 250°C. Finally, the IGZO film with a vertically gradient Ga, Zn, In diffusion is obtained and used as the channel layer of TFTs. The results showed that the novel method lead to an improvement in charge carrier mobility and an improvement in the on-off current ratio of IGZO TFTs along with an improved stability. Compared with those for con-IGZO TFTs, the mobility for vd-IGZO TFT reaches 2.81cm2 V−1 s−1 from 0.88cm2 V−1 s−1, the threshold voltage(Vth) changes from 3.7V to 0.3V, the sub-threshold swing (S.S) decreases from 0.51V/dec to 0.35V/dec, and the on-current/off-current (Ion/Ioff) increases from 2.1 × 106 to 2.3 × 107. Besides, the positive bias stress (PBS), negative bias stress (NBS) and environmental stability are all improved to some extent. Hence this novel vertical diffusion method shows great potential to be applicable in the fabrication of flexible TFT.

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( $V_{\mathrm{ G}}$ )/positive drain bias ( $V_{\mathrm{ D}}$ ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( $V_{\mathrm {\mathbf {th}}}$ ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{ S}}= 0$ V) and ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 0$ V, and $V_{\mathrm{S}}= 15$ V) under light illumination, it is found that the negative $V_{\mathrm {\mathbf {th}}}$ shift is affected only by $V_{\mathbf {G}}$ , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by $V_{\mathrm{D}}$ -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( $C_{\mathrm {\mathbf {GD}}}$ ) was measured before/after the ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{S}}= 0$ V) stress to clarify the presence and distribution of the drain-side trapped holes. From $C_{\mathrm {\mathbf {GD}}}$ stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress.

We propose the introduction of a magnesium oxide (MgOx) layer to reduce the temperature required for the activation of indium gallium zinc oxide (IGZO) thin films. By incorporating the MgOx layer between the IGZO channel layer and the gate insulator layer, the required activation temperature is lowered from 300 to 200 °C while enhancing the electrical performance of the IGZO thin-film transistor (TFT). Specifically, the field effect mobility is improved from 6.40 to 16.12 cm2/(V s), the on/off current ratio is enhanced from 1.62 × 109 to 7.16 × 109, and subthreshold swing is enhanced from 0.48 to 0.46 V/decade. Furthermore, IGZO TFTs with the MgOx layer exhibit enhancements in threshold voltage (VTH) shift compared to TFTs without the MgOx layer under positive bias stress (VGS = 20 V and VDS = 0.1 V for 10,000 s) and negative bias stress (VGS = -20 V and VDS = 0.1 V for 10,000 s): the VTH shifts are decreased from 2.40 to 1.72 V and from 0.56 to 0.53 V, respectively. These enhancements are verified through various analyses and are attributed to the diffusion of Mg atoms into the IGZO front channel during the low-temperature activation process, which results in the formation of Mg-doped IGZO between the MgOx and IGZO channel layers.

We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs) with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP) and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC) bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (VT), subthreshold slope (S), mobility (μ), onset voltage (Von) and Ion/Ioff ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the μ, Ioff current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.