Low-voltage solution-processed NaxCu1−xI thin-film transistors for mimicking synaptic plasticity

Electrical instabilities of a-IGZO TFTs under different conditions of bias and illumination stress

Electrical stability of pentacene thin film transistors

Optoelectronic synaptic devices outperform electrical synapses in speed, energy efficiency, and integration density. Recent progress in visual sensing and optogenetics has led to the integration of light-sensitive materials in these devices, promising unmatched speed, connectivity, and bandwidth. Here, we present a copper phthalocyanine (CuPc) based optoelectronic synaptic device boasting femto Joule power consumption stable at room temperature. The optoelectronic synapse can be operated with energy consumption as low as 430.4 fJ which is very attractive from the point of view of low-power neuromorphic devices. By modulating light pulses, the neuromorphic behavior can be emulated including excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), transitioning from short-term plasticity (STP) to long-term plasticity (LTP), spike-rate dependent plasticity (SRDP) and spike-number dependent plasticity (SNDP), etc. Optical potentiation and electrical depression are observed with combined optical and electrical stimulation, proving the multi-functionality of the synapse. Furthermore, the device demonstrates classical associative learning behaviors like Pavlovian conditioning using optical and electrical stimuli. We have established the pain conditioning processes such as hyperalgesic response and pain extinction effects with varying optical pulse amplitudes. These results render the CuPc-based devices as multifunctional and highly versatile artificial synaptic devices for future computing applications, offering unprecedented efficiency and functionality in neuromorphic systems.

Here, we report investigations of the effects of bias stress on the density of states (DOS) in polymer thin-film transistors (PTFTs). As the active channel layer, these PTFTs employed an inkjet-printed semiconducting film of P8T2Z-C12 [poly (tetryldodecyloctathiophene-alt-didodecyl bithiazole)]. In positive bias stress tests, the threshold voltage (VT) of the inkjet-printed PTFT shifted in the positive direction. However, this shift was largely recovered when the PTFT was released from the bias stress. We analyzed the effect of the bias stress manifested by the VT shift using the full energy range of the subgap DOS versus the duration of the bias stress, which we obtained by applying various DOS extraction techniques.

Emulating neurons/synapses in the brain is an important step to realizing highly efficient computers. This fact makes neuromorphic devices important emerging solutions to the limitations imposed by the current computing architecture. To mimic synaptic functions in the brain, it is critical to replicate ionic movements in the nervous system. It is therefore important to note that ions move easily in liquids. In this study, we demonstrate a liquid-based neuromorphic device that is capable of mimicking the movement of ions in the nervous system by controlling Na+ movement in an aqueous solution. The concentration of Na+ in the solution can control the ionic conductivity of the device. The device shows short-term and long-term plasticity such as excitatory postsynaptic current, paired-pulse facilitation, potentiation, and depression, which are key properties for memorization and computation in the brain. This device has the potential to overcome the limitations of current von Neumann architecture-based computing systems and substantially advance the technology of neuromorphic computing.

Inkjet‐printed indium‐tin‐oxide (ITO) synaptic thin‐film transistors (TFTs) using solution‐processed high‐k zirconium oxide (ZrOx) gate dielectric layer are reported. The effect of ZrOx annealing temperature from 300 to 500 °C on the TFT performance is investigated. The optimized ZrOx gate dielectric layer of the ITO TFT can mimic biological synaptic response for the realization of intelligent computers and artificial bionic brain. The strong synaptic behavior of the ITO TFT exhibiting the on/off current ratio of ≈106 can be obtained at the ZrOx annealing temperature of 300 °C. The amount of hydroxyl (OH) groups in the dielectric film can be a crucial factor for the formation of an electric double layer (EDL) on the top region of the gate dielectric. The device exhibits the excitatory post‐synaptic current (EPSC), inhibitory postsynaptic current (IPSC), and paired‐pulse facilitation (PPF). Therefore, the inkjet‐printed ITO TFT using printed ZrOx gate dielectric can be used for low‐cost synaptic TFTs.

Various hippocampal and neocortical synapses of mammalian brain show both short-term plasticity and long-term plasticity, which are considered to underlie learning and memory by the brain. According to Hebb’s postulate, synaptic plasticity encodes memory traces of past experiences into cell assemblies in cortical circuits. However, it remains unclear how the various forms of long-term and short-term synaptic plasticity cooperatively create and reorganize such cell assemblies. Here, we investigate the mechanism in which the three forms of synaptic plasticity known in cortical circuits, i.e., spike-timing-dependent plasticity (STDP), short-term depression (STD) and homeostatic plasticity, cooperatively generate, retain and reorganize cell assemblies in a recurrent neuronal network model. We show that multiple cell assemblies generated by external stimuli can survive noisy spontaneous network activity for an adequate range of the strength of STD. Furthermore, our model predicts that a symmetric temporal window of STDP, such as observed in dopaminergic modulations on hippocampal neurons, is crucial for the retention and integration of multiple cell assemblies. These results may have implications for the understanding of cortical memory processes.

Thin-film transistors (TFTs) that utilize oxide semiconductors as channel materials have been widely used in various electronic device applications, such as displays, sensors, and memory devices. Among the oxide semiconductors, transparent amorphous indium-gallium-zinc oxides (a-IGZO) have superior characteristics, namely, high field-effect mobility (~10cm2/Vs), good uniformity, low processing temperatures, optical transparency, and low-cost fabrication processability compared with conventional amorphous/poly-silicon TFTs. However, oxide TFTs including a-IGZO TFTs have bias stress-induced instabilities, which are still critical issues in launching commercial oxide TFT products. These issues can be attributed to the oxygen vacancy-related defects, which are known to act as a major source of electrons and as carrier traps. To suppress such oxygen vacancy-related defects, many researchers reported various techniques, such as ozone treatment, oxygen annealing on oxide TFTs, passivation, and metal-doped oxide semiconductors.In this study, we investigated the device performance of tantalum (Ta)-doped IGZO TFTs as a function of Ta content. Ta was used as a dopant because of its bond-dissociation-energy (BDE, 805kJ/mol) with oxygen higher than those of In, Ga, and Zn. The Ta-doped IGZO, which was adopted as a channel layer of bottom-gate TFTs, was fabricated using a magnetron co-sputtering method. Heavily doped p-type Si wafer with thermally grown SiO2 (300nm) was used as substrates. The RF power for the a-IGZO (In2O3 :Ga2O3 : ZnO = 1:1:1)target was fixed at 100 W while the power for the Ta target increased from 0 to 50 W. Aluminum (Al) was deposited as source/drain electrodes using an electron beam evaporator. With increasing Ta content in the IGZO films, the field-effect mobility (μFE) of the Ta-doped IGZO TFTs decreased, the threshold voltage (Vth) increased from negative to positive values, and the subthreshold swing (SS) became smaller with higher on/off ratio. Especially, Ta (10W)-doped IGZO TFTs exhibited μFE of 7.11 cm2/Vs, a SS of 0.195V/decade, and an on/off ratio ~1x108. These results show that the Ta-doping improves the switching characteristics of the Ta-IGZO TFTs. Furthermore, to evaluate the bias-stress stability, positive bias stress (PBS), negative bias stress (NBS) tests were conducted.

In recent years, environment-friendly and biocompatible electronics have received extensive attention. As a kind of natural biological material with rich sources, proteins have been widely used in electronic devices. In this work, electric-double-layer (EDL) thin-film transistors (TFTs) gated by natural chicken albumen are fabricated at room temperature. The indium-tin-oxide (ITO) conductive glass is employed as a substrate. The spin coated chicken albumen film is used as the gate dielectric. The indium-zinc-oxide (IZO) is sputtered on an albumen-coated ITO glass as the channel and the source/drain electrodes with only one shadow mask. The capacitance-frequency measurements demonstrate an ultra-large specific capacitance of the albumen film at low frequencies. For the physical understanding of the capacitive coupling within the albumen film, the phase angle is characterized as a function of frequency. The results indicate that such an ultra-large capacitive coupling can be attributed to the proton migration under the electric field, which results in the EDL effect at the interface of the albumen film. By DC sweep measurements, a low leakage current is observed (<3.0 nA at <i>V</i><sub>gs</sub>=1.5 V), which indicates a good isolation of the albumen-based dielectric. By transfer and output measurements, an ultralow operation voltage of 1.5 V, a high field-effect mobility of 38.01 cm<sup>2</sup>/(V·s), a low subthreshold swing of 164 mV/decade, and a large on-off ratio of 2.4×10<sup>6</sup> are obtained for such albumen-gated TFTs. The ultra-large EDL capacitive coupling is responsible for such good electrical characteristics. The dynamic bias stress stability of the albumen-gated TFTs is also investigated. The device exhibits a good reproducibility in response to the repeatedly pulsed gate voltage. A maintainable on-to-off ratio (>10<sup>6</sup>) and no obvious current loss are observed, which suggests that neither chemical doping nor chemical reaction occurs at the albumen-based dielectric/IZO channel interface when the gate potential is biased. After being aged one day in air ambient without surface passivation, the albumen-gated TFTs show a good stability of the electrical properties. Such ultralow-voltage EDL-TFTs gated by albumen electrolyte will be useful for the bioelectronic and low-energy portable electronic products. And our results will also have potential applications in biocompatible artificial neuron networks and brain-inspired neuromorphic systems.

Amorphous InGaZnO (a-IGZO) has attracted a lot of attention as a high-mobility channel material for thin film transistors (TFTs). However, the instability mechanism involving threshold voltage and subthreshold swing (SS) in a-IGZO TFTs still requires further investigation. In this study, we investigated the electrical instability of amorphous InGaZnO TFTs subjected to alternating positive and negative bias stresses. Based on the respective mechanisms under positive and negative bias stresses, including ionization and spatial movement of oxygen vacancies, bi-directional threshold voltage shifts were observed under alternating bias stress. The SS values vary with the bias stress polarity, reflecting the presence and distribution of oxygen vacancies. Our findings reveal a complementary mechanism based on oxygen vacancies, elucidating the behavior under complex bias stress schemes and extending our understanding of instability mechanisms beyond monotonous bias stress.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔVTH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔVTH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (CGD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage VFB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

The effects of the annealing temperature on the structural and chemical properties of soluble-processed zinc-tin-oxide (ZTO) films were examined by transmission electron microscopy, atomic force microscopy, high resolution X-ray reflectivity, and X-ray photoelectron spectroscopy. The density and purity of the resulting ZTO channel layer increased with increasing annealing temperature, whereas the oxygen vacancy defect density decreased. As a result, the device performance of soluble ZTO thin film transistors (TFTs) was improved at higher annealing temperature. Although the 300 °C-annealed ZTO TFT showed a marginal field-effect mobility (μFE) and high threshold voltage (Vth) of 0.1 cm(2)/(V s) and 7.3 V, respectively, the 500 °C-annealed device exhibited a reasonably high μFE, low subthreshold gate swing (SS), Vth, and Ion/off of 6.0 cm(2)/(V s), 0.28 V/decade, 0.58 V, and 4.0 × 10(7), respectively. The effects of dark negative bias stress (NBS) and negative bias illumination stress (NBIS) on the degradation of transfer characteristics of ZTO TFTs were also investigated. The instability of Vth values of the ZTO TFTs under NBS and NBIS conditions was suppressed with increasing annealing temperature. To better understand the charge trapping mechanism, the dynamics of Vth shift with NBS and NBIS time for all ZTO TFTs was analyzed on the basis of the stretched exponential relaxation. The negative Vth shift for each transistor was accelerated under NBIS conditions compared to NBS, which resulted in a higher dispersion parameter and smaller relaxation time for NBIS degradation. The relaxation time for NBS and NBIS instability increased with increasing annealing temperature, which is discussed on the basis of the transition mechanism of oxygen vacancy defects.

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( $V_{\mathrm{ G}}$ )/positive drain bias ( $V_{\mathrm{ D}}$ ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( $V_{\mathrm {\mathbf {th}}}$ ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{ S}}= 0$ V) and ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 0$ V, and $V_{\mathrm{S}}= 15$ V) under light illumination, it is found that the negative $V_{\mathrm {\mathbf {th}}}$ shift is affected only by $V_{\mathbf {G}}$ , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by $V_{\mathrm{D}}$ -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( $C_{\mathrm {\mathbf {GD}}}$ ) was measured before/after the ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{S}}= 0$ V) stress to clarify the presence and distribution of the drain-side trapped holes. From $C_{\mathrm {\mathbf {GD}}}$ stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress.

In this study, we propose the use of artificial synaptic transistors with coplanar-gate structures fabricated on paper substrates comprising biocompatible and low-cost potato-starch electrolyte and indium-gallium-zinc oxide (IGZO) channels. The electrical double layer (EDL) gating effect of potato-starch electrolytes enabled the emulation of biological synaptic plasticity. Frequency dependence measurements of capacitance using a metal-insulator-metal capacitor configuration showed a 1.27 μF/cm2 at a frequency of 10 Hz. Therefore, strong capacitive coupling was confirmed within the potato-starch electrolyte/IGZO channel interface owing to EDL formation because of internal proton migration. An electrical characteristics evaluation of the potato-starch EDL transistors through transfer and output curve resulted in counterclockwise hysteresis caused by proton migration in the electrolyte; the hysteresis window linearly increased with maximum gate voltage. A synaptic functionality evaluation with single-spike excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), and multi-spike EPSC resulted in mimicking short-term synaptic plasticity and signal transmission in the biological neural network. Further, channel conductance modulation by repetitive presynaptic stimuli, comprising potentiation and depression pulses, enabled stable modulation of synaptic weights, thereby validating the long-term plasticity. Finally, recognition simulations on the Modified National Institute of Standards and Technology (MNIST) handwritten digit database yielded a 92% recognition rate, thereby demonstrating the applicability of the proposed synaptic device to the neuromorphic system.

Zinc‐based metal oxide semiconductors have attracted attention as an alternative to current silicon‐based semiconductors for applications in transparent and flexible electronics. Despite this, metal oxide transistors require significant improvements in performance and electrical reliability before they can be applied widely in optoelectronics. Amorphous indium–zinc–tin oxide (a‐IZTO) has been considered an alternative channel layer to a prototypical indium–gallium–zinc oxide (IGZO) with the aim of achieving a high mobility (>40 cm2 Vs−1) transistors. The effects of the gate bias and light stress on the resulting a‐IZTO field‐effect transistors are examined in detail. Hydrogen impurities in the a‐IZTO semiconductor are found to play a direct role in determining the photo‐bias stability of the resulting transistors. The Al2O3‐inserted IZTO thin‐film transistors (TFTs) are hydrogen‐poor, and consequently show better resistance to the external‐bias‐thermal stress and photo‐bias‐thermal stress than the hydrogen‐rich control IZTO TFTs. First‐principles calculations show that even in the amorphous phase, hydrogen impurities including interstitial H and substitutional H can be bistable centers with an electronic deep‐to‐shallow transition through large lattice relaxation. The negative threshold voltage shift of the a‐IZTO transistors under a negative‐bias‐thermal stress and negative‐bias‐illumination stress condition is attributed to the transition from the acceptor‐like deep interstitial Hi− (or substitutional H‐DX−) to the shallow Hi+ (or HO+) with a high (low) activation energy barrier. Conclusively, the delicate controllability of hydrogen is a key factor to achieve the high performance and stability of the metal oxide transistors.