Electromigration behavior of interconnects between chip and board for embedded wafer level ball grid array (eWLB)

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

In this paper, we present a 28 GHz antenna array in package which covers the n257 and n258 frequency bands designated for 5G applications. The dipole antenna array is placed on one of the two re-distribution layers in the fan-out eWLB (embedded Wafer Level Ball Grid Array) package. For TX and RX, separate but identical antenna arrays are placed on each side of the die. The paper presents a novel horn-shaped heatsink which not only dissipates the heat, but also improves the radiation performance. The four-elements dipole array has the impedance bandwidth of almost 6 GHz (24–30 GHz) and shows a maximum realized gain of 9.5 dBi. Beam-steering in ± 35 deg is achieved in the azimuth plane (H-plane) by providing different phases to the dipoles through the chip. The measurements nicely agree with the simulation results.

In this article, we present a study about the impact of embedded wafer level ball grid array (eWLB) on characteristics of antenna. The antenna in package is a promising solution for integration of antennas and eWLB technology enables integration of passive components and antennas into the redistribution layer (RDL). The antenna radiates perpendicular to the package in broadside into the package. There are different parameters such as size, shape, and thickness of the eWLB package which affect the radiation pattern significantly. Moreover, the materials properties of package like relative permittivity (ε <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ) and loss tangent (tanδ) impact the impedance bandwidth, gain and efficiency of antenna and have to be taken into account. The other important parameter to design the antenna in package is the distance of antenna to the reflector. We present the feasibility of an antenna with backside metallization as an integrated reflector in an 8 mm × 8 mm eWLB package. The measurement and simulation results show that eWLB is an attractive candidate for mm-wave applications.

The emergence and evolution of any package technology is driven by market trends as experienced by the end application. With the maturation of the mobile market, the trends for Smartphone and other mobile devices are more than ever for lower cost. Meanwhile, a higher degree of functionality and performance, thinner profile, and longer battery life are some of the additional market drivers seen in these devices. The implications of these market drivers on the packaging content of mobile devices are, higher performance designs, lower cost, smaller form factor, and higher level of integration. The advancement of silicon scaling to 14/16 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. Earlier in 2012, eWLB Package-on-Package (eWLB-PoP) technology delivered a 30% height reduction in PoP, reducing the overall stacked package height from the industry standard 1.4mm to 1.0mm. Through further innovations in eWLB technology, a 40% height reduction in the bottom PoP architecture has been achieved. An ultra thin z-height of 0.3mm was realized in 2013, thereby providing the advantage of having an overall PoP package height as low as 0.8mm with proven board level reliability. While traditional PoP solutions are widely used in the high-end mobility market, demand is accelerating for ultra thin, cost effective packages that have the flexibility to serve a range of applications from mid-range to low-end mobile phones as well as tablets that require significantly higher processor speeds. While printed circuit board (PCB) substrate technology limits the interconnection density of a PoP package to 200-300 input/output (I/O), eWLB-based PoP solutions can deliver beyond 500 I/O in an overall thinner package with a dense vertical interconnection and wider interface to stack memory packages on the top. This paper reports developments that extend 3D PoP and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Various test vehicles have been designed and fabricated to demonstrate these low profile solutions for mobile, portable and wearable electronics. The test vehicles have ranged from medium to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including embedded Bar (eBar), laser ablation, interconnect processes and mechanical characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on 3D eWLB-PoP / eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided. The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance. For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes. For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.

Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2]. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3]. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.

System-in-Package (SiP) concept has been adopted from a system-on-board practice when board-space is a concern. This is very applicable for mobile and wearable applications. Moving many devices/components into a small area would reduce the interconnection lengths between components/devices, and therefore reduce the overall size. But it does not automatically yield good results, as it may increase EMI (electromagnetic interference) between components/devices. To have short cycle-times for package development, strong electrical skills are required for SiP designs. For wafer-level SiP, as finer design rules and thinner dielectric are available for designs, further size-reduction is greatly expected. But EMI or cross-talk could be much more severe. The performance verification is needed to be more on EMI or cross-talk rather than on interconnection RCL parasitic, after individual components/chips are made as known-good-dies electrically. In an embedded Wafer Level Ball Grid Array (eWLB), as there are no bumps (or Cu-column) at the die side and the dielectric substrate is much thinner than laminate substrate, its thermal performance is typically better than incumbent fc-FBGA, due to short thermal path. Successfully-made eWLB modules can achieve super electrical and thermal performance, where thin profiles and small form factors are required. In this paper, we describe the advantages of using eWLB for system-level integration through several examples, such as, 2D integration with multiple-dies, and 3D integration for high-speed and high-frequency. Area reductions and performance trade-off, along with other key features, are discussed in these examples.

Recently, the technology of wireless sensor networks (WSNs) experiences a growing use in home automation or advanced industry infrastructure applications. Despite a strong interest of industries in this technology, key issues like miniaturization and security of WSN nodes has not been solved yet. State-of-the-art WSN nodes do not provide credible security nor satisfying configurability and miniaturized implementations. This publication deals with these limitations and presents a WSN node that provides security, configurability, and a miniaturized design. To show the sensor node feasibility, the WSN node is implemented within a smart home demonstrator. Additionally, a miniaturized pre-study WSN node design is presented using the novel embedded wafer level ball grid array (eWLB) packaging technology. Furthermore, an eWLB based WSN node design is proposed that further miniaturize the presented WSN node.

An overview of the SiGe technologies used at Infineon Technologies for radar applications will be given. The production of bare-die chips started in 2009 using the bipolar technology B7HF200. Since 2012 packaged MMICs in an embedded wafer level ball grid array (eWLB) are available. Process challenges and solutions for radar chips in an eWLB package are presented. Examples of commercial SiGe radar chips in production are shown. Furthermore Infineon’s next generation BiCMOS technology B11HFC with fT of 250 GHz and fmax of 370 GHz is described. In addition, significant improvements of the cut-off frequencies can be achieved by replacing the currently used double-poly self-aligned configuration by a more advanced SiGe HBT architecture like IHP’s transistor module with selective base link epitaxy. The capability of this transistor cell for future BiCMOS generations was demonstrated by integrating it into Infineon’s 130 nm CMOS process. A transistor performance with fmax of 500 GHz was achieved.

This paper investigates the feasibility of a gain enhancement technique using stacked directors for antennas in package. A 77-GHz antenna designed for automotive radar applications and a frequency multiplier were integrated in a 6×6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> embedded wafer level ball grid array (eWLB) package. The frequency multiplier generates the eighteenth harmonic of its input signal and allows the use of a commercial signal source to characterize the antenna. Parasitic directors were etched on a low-loss 2.54mm thick RT/duroid 5880 LZ laminate by means of photolithography and were mounted on the eWLB package. Theoretical analysis and full electromagnetic simulations were verified against the actual measurements of the antenna radiation beam pattern.

The fan-out Wafer Level Package Technology (FO-WLP) eWLB (Embedded Wafer Level Ball Grid Array) is a recent Advanced Packaging technology that was initially developed by Infineon Technologies with reconstituted 8″ wafers, and has ramped-up to high volume production since 2009. In a joint development project between Infineon Technologies and NANIUM in 2010, this packaging technology was successfully extended to reconstituted 300mm (12″) wafers for high volume production. NANIUM is producing now under license of IMC (Intel Mobile Communications), the former Wireless Solutions Business Unit of Infineon Technologies. This step enabled a cost advantage position for eWLB compared to other packaging technologies. eWLB is gaining wider market acceptance, but has been restricted up to now to wireless applications leveraged by its advantages regarding performance, form factor and cost. Deploying its innumerous additional advantages, like design and integration flexibilities; thermal and electrical performance; reliability and robustness, NANIUM has started recent R&amp;D projects with different customers with joint goals to enable eWLB on other applications to enter new markets. Some of those projects reached already the milestone “Engineering Samples available”. The paper will present an overview of those new applications, where NANIUM sees eWLB gaining momentum.

In this article we present an antenna array concept in embedded wafer level ball grid array (eWLB) package for mm-wave applications. The eWLB package has a excellent performance for high frequency and the additional fan-out area around the silicon chip enables the realization of passives and antennas. Moreover, integration of the antenna in package increases the efficiency and reduces cost. For some applications a single antenna in package is unable to achieve the required gain and directivity. Combining several antenna elements as an array in a package can be a possible solution. A two elements differential dipole antenna array in an 8 mm × 8 mm eWLB package at IMS (Industrial, Medical and Scientific) band about 61 GHz is analyzed and successfully implemented. A 100 Ω differential feeding system is designed for the array. The measured reflection coefficient is -25 dB and the designed antenna array has a gain of 11 dB and radiates in broadside.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Advanced packaging challenges standard metrology means, notably optical profilers, by shrinking dimensions and spacings between interconnect (RDL, Bump, via). New needs such as die flatness and roughness also raise up due to the critical requirement of robust stacking into complex 3D assembly. Challenges translate into demand for both higher lateral and vertical resolution. In this talk, we will introduce optical profiler based on White Light Interferometry principle (WLI) which has inherent advantages combining lateral resolution below micron level as well as providing sub-nanometer vertical resolution at all magnifications. We will explain how this technology can not only provide solution for current Re-Distribution Layer (RDL), bump and Under Bump Metallization (UBM) but also scope through new development with future roadmap. Talk will further develop topics into two main directions. The first one consists on studying or monitoring the low roughness of die and supporting sacrificial wafer in case of Chip-on-Wafer-on-Substrate (CoWos). Roughness indeed plays key role in adequate adhesion between die and wafer on top of possible impact from surface contamination. Curvature of die can also trigger issues during anchoring process for which control of overall die shape is beneficial. In both cases, WLI optical profiler fulfills stringent metrology via sub-nanometer vertical resolution along large field of view. Throughput and 10’s picometer (pm) repeatability are then compatible with inline control through integration of wafer handler. The second direction will focus on panel level integration with measurement on next generation RDL. We will illustrate how large optical platform can scope with 600mm by 600 mm panel and provide metrology for Critical Dimensions on RDL. Notably, we will present evidences of metrology capability for 1µm and 0.8µm RDL technology by using newly developed super-resolution algorithm. This algorithm allows 2x enhancement regarding lateral resolution making possible measurement of high dense RDL or bump array. Finally, we will present data regarding high aspect ratio Through Silicon Via (TSV) with regular objective up to 1:20. WLI technology uniquely provides technical advantages such as combination of parallel light injection, ability to scope with weak signals and nanometer repeatability. Conclusion will open possible expansion of technology to measure with high throughput PhotoResist (PR) layer thickness as well as thin insulative oxide layer.