Embedded Architecture Description Language

Implementing and debugging high-performance network subsystems is a challenging task. In this paper, we present our experiences from developing and debugging a network interface card (NIC). Our NIC targets networked storage subsystems (Marazakis et al., 2006). For this purpose it mainly provides support for remote direct-memory-access (RDMA) write, sender-side notification of RDMA write completion, and receiver-side interrupt generation. In our work we examine issues that arise during system implementation and debugging, both in terms of correctness as well as performance. We present an analysis of the individual problems we encounter and we discuss how we address each case. For most problems we encounter, it is not possible to rely on existing debugging tools. However, we find that most of the techniques we use in this process, rely on collecting some form of event records from software or hardware components. We believe that such capabilities can be provided for independent hardware or software components in isolation, a fairly straight-forward task, thus, significantly simplifying the debugging process in complex systems of this nature

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

MOPS is a platform for surgical robotics research. It consists of hardware and software components for building surgical robot systems based on existing robot arms. The reference system presented in this paper has two robot arms, each with an adapter for mounting and actuating different types of surgical instruments. Additionally, the system has a high-resolution stereo camera and a simple operator console with haptic devices and foot pedals for teleoperating the manipulators. Software components are based on Robot Operating System (ROS) to keep them modular and reusable for different types of hardware. We evaluate the precision of our system for vision-based tasks and demonstrate its potential for surgical task automation. The mean end-to-end error, including that of the vision system, for a trajectory following task was 1.2mm / 0.3° for one manipulator and 2.7mm / 0.7° for the other. MOPS software and hardware components are made available under an open-source license to encourage collaboration and facilitate the advancement of surgical robotics research.

The public transport system of New South Wales (NSW), Australia is impotent to receive 100% of the fare from light rail and buses due to the unavailability of a continuous real-time monitoring system. This scheme thereby seeks to help update the NSW public transport ticket collection system, with the aid of a counter that will be integrated into the public transportation within the Ticket Tapping Machine, to provide passenger count against the number of touches occurring at each stop; and thus, increasing the revenue. The product comprises of hardware and software components - the hardware system is located within the public transport while the software system incorporating a web portal is positioned for the authorities to have access to the real-time passenger data. At the hardware end, the ultrasonic sensors and the raspberry pi would detect the number of passengers on the transport and the LCD screen would display the number of passengers who had not tapped their smart card ticket. Additionally, the raspberry pi module used in the hardware component can denote the transportation location with the help of an in-built Wi-Fi component. With this designed technology, the authorities would be able to monitor and record the movements of the passenger in real-time system addressing the existing challenges faced by the NSW public transport authority, especially in the case of light rail and buses being used for free by certain passengers.

This paper aims to describe the development of a safety solution for an omnidirectional autonomous mobile robot actuated by permanent magnet synchronous machines drives that performs numerous tasks in logistics environments. This is done with specific equipment that ensures a level of safety integrity of type SIL2 or SIL3 according to the IEC 61508 standard, which certifies certain parameters such as probability of dangerous failure on request, risk reduction factor and hourly probability of hazardous malfunctions. The safety system implemented in autonomous mobile robot is a mix between hardware components(locomotion system, perception system, and decision controllers) and software components that use the information from the perception system to generate commands for the locomotion system.

Preface. 1. Introduction. 1.1 What is COP? 1.2 Why is COP important? 1.3 What is a component? 1.4 Hardware components and software components. 1.5 From OOP to COP. 1.6 Component-based software engineering. 1.7 Summary. 1.8 Self-review questions. 1.9 Exercises. 2. A Theory of Components. 2.1 Principles of COP. 2.2 Infrastructures of COP. 2.3 Component models. 2.4 Connection models. 2.5 Deployment models. 2.6 Unifying component technologies. 2.7 Summary. 2.8 Self-review questions. 2.9 Exercises. 3. COP with JavaBeans. 3.1 Overview of JavaBeans technology. 3.2 The component model of JavaBeans. 3.3 The connection model of JavaBeans. 3.4 The deployment model of JavaBeans. 3.5 Examples and lab practice. 3.6 Summary. 3.7 Self-review questions. 3.8 Exercises. 4. Enterprise JavaBeans Components. 4.1 The EJB a rchitecture. 4.2 The component model of EJB. 4.3 The connection model of EJB. 4.4 The deployment model of EJB. 4.5 Examples and lab practice. 4.6 Summary. 4.7 Self-review questions. 4.8 Exercises. 4.9 Programming exercises. 5. CORBA Components. 5.1 The COBRA component infrastructure. 5.2 The CORBA component model (CCM). 5.3 The connection model of CORBA and CCM. 5.4 The deployment model of CORBA and CCM. 5.5 Examples and lab practice. 5.6 Summary. 5.7 Self-review questions. 5.8 Exercises. 5.9 Programming exercises. 6. .NET Components. 6.1 The .NET framework. 6.2 The component model of .NET. 6.3 The connection model of .NET. 6.4 .NET component deployments. 6.5 Visual Studio .NET. 6.6 Examples and lab practice. 6.7 Summary. 6.8 Self-review questions. 6.9 Exercises. 6.10 Programming exercises. 7. COP with OSGi Components. 7.1 Overview of OSGi technology. 7.2 The component model of OSGi. 7.3 The connection model of OSGi. 7.4 The deployment model of OSGi. 7.5 Examples and lab practice. 7.6 Summary. 7.7 Self-review questions. 7.8 Exercises. 8. Web Services Components. 8.1 The Web Services framework. 8.2 The component model of Web Services. 8.3 The connection model of Web Services. 8.4 Web Services component deployment. 8.5 Examples and lab practice. 8.6 Summary. 8.7 Self-review questions. 8.8 Exercises. 8.9 Programming exercises. Appendix.

As the development of technology, the mobile phone world also has developed very quickly. Mobile communication and services, over emerging wireless technologies, provide anyone, anytime and anywhere access. Moreover, the intelligence is now often embedded into modern applications, such as surveillance and supervising systems. This work presents an intelligent and a pervasive supervising platform for information system (IS) security based on multi-agent systems (MAS) which detects and classifies malware events that occurs on software and hardware components and sends real time notification to smart phone users. The proposed platform is formed by two components: The first one consists of a Central Software Component (CSC); the supervisor application that manages devices and evaluates logs and alarms of the supervised components. The second one consists of an Embedded Software Component (ESC) on the Mobile Device (MD) with an ANDROID OS. In our platform, we have implemented agents on ESC using JADE-LEAP android, note that the ESC is targeted to smart phones and tablet that run the operating system Android, JADE API on CSC and the communication between these two components is performed using the Secure Socket Layer (SSL) protocol implemented using the JADE-S plug-in.

Commodity DRAM-based processing-using-memory (PuM) techniques that are supported by off-the-shelf DRAM chips present an opportunity for alleviating the data movement bottleneck at low cost. However, system integration of these techniques imposes non-trivial challenges that are yet to be solve d . Potential solutions to the integration challenges require appropriate tools to develop any necessary hardware and software components. Unfortunately, current proprietary computing systems, specialized DRAM-testing platforms, or system simulators do not provide the flexibility and/or the holistic system view that is necessary to properly evaluate and deal with the integration challenges of commodity DRAM-based PuM techniques. We design and develop Processing-in-DRAM (PiDRAM), the first flexible end-to-end framework that enables system integration studies and evaluation of real, commodity DRAM-based PuM techniques. PiDRAM provides software and hardware components to rapidly integrate PuM techniques across the whole system software and hardware stack. We implement PiDRAM on an FPGA-based RISC-V system. To demonstrate the flexibility and ease of use of PiDRAM, we implement and evaluate two state-of-the-art commodity DRAM-based PuM techniques: (i) in-DRAM copy and initialization (RowClone) and (ii) in-DRAM true random number generation (D-RaNGe) . We describe how we solve key integration challenges to make such techniques work and be effective on a real-system prototype, including memory allocation, alignment, and coherence. We observe that end-to-end RowClone speeds up bulk copy and initialization operations by 14.6× and 12.6×, respectively, over conventional CPU copy, even when coherence is supported with inefficient cache flush operations. Over PiDRAM’s extensible codebase, integrating both RowClone and D-RaNGe end-to-end on a real RISC-V system prototype takes only 388 lines of Verilog code and 643 lines of C++ code.

The partitioning between hardware (HW) components and software (SW) components plays a major role in the codesign process of Embedded Systems (ES). Defining a good partitioning at early stage of the design allows improving the system performance, meeting the time to market and optimizing several other metrics. The majority of works made a focus on execution time and hardware area metrics while dealing with the hardware software partitioning (HSP) problem, and in some cases the power consumption metric was also taking in consideration. In this paper, we propose a novel approach in order to optimize simultaneously several metrics while respecting a constraint on global hardware area. The proposed approach is implemented using 0–1 Knapsack Problem (KP) algorithm. Experimental results show that the proposed algorithm is very fast and gives more reliable solutions comparing to Genetic Algorithm (GA) and Simulated Annealing (SA) algorithm.

This paper presents an accelerated implementation of the Vector Directional Filter (VDF) on a Field Programmable Gate Array (FPGA) for real-time denoising of color images. The VDF effectively suppresses noise while preserving edges and fine details, making it ideal for a range of applications such as satellite and multispectral biomedical imaging. However, the filter's high computational complexity poses challenges for real-time processing. Existing solutions either fail to meet real-time execution requirements or compromise image quality through hardware implementation approximations. To overcome these challenges, we first model the VDF using C/C++ programming, and subsequently design an efficient floating-point hardware architecture employing the High-Level Synthesis (HLS) flow. Optimal directives are selected using the Xilinx Vivado HLS tool. The VDF architecture is then integrated as a coprocessor with the Cortex-A53 hardcore processor in the XCZU9EG FPGA. To enhance data bandwidth between software and hardware components, three Direct Memory Access (DMAs) units are utilized to transfer three image lines in parallel. Furthermore, internal memory is implemented on the XCZU9EG FPGA, providing increased flexibility for managing the restored image. The VDF Software/Hardware (SW/HW) design's robustness and accuracy are validated through experimental studies on the ZCU102 board. Our design accelerates the filtering process by 21 times, maintaining visual quality and effectively removing noise from color images compared to the VDF SW design. Additionally, our solution outperforms existing approaches in terms of filtered image quality and processing time, showing a 24% improvement in the worst-case scenario.

The attendance recording system is expected to provide data visualization to detect students who have attendance problems. The system consists of hardware and software components. The hardware components are data acquisition devices that can record student's attendance based on fingerprint identification. In addition to identifying users, the devices also perform registration and managing user identity data storage for identification purposes. This paper will discuss about the detail system design and implementation of the attendance recording devices, starts from an explanation of the general system architecture, then brief description about the subsystem for identification, registration, and data management on the device, and lastly the implementation and integration of overall system on the device.

Modern systems are enormously complex; many applications today comprise millions of lines of code, make extensive use of software frameworks, and run on complex, multi‐tiered, run‐time systems. Understanding the performance of these applications is challenging because it depends on the interactions between the many software and the hardware components. This paper describes and evaluates an interactive and iterative methodology, temporal vertical profiling, for understanding the performance of applications. There are two key insights behind temporal vertical profiling. First, we need to collect and reason across information from multiple layers of the system before we can understand an application's performance. Second, application performance changes over time and thus we must consider the time‐varying behavior of the application instead of aggregate statistics. We have developed temporal vertical profiling from our own experience of analyzing performance anomalies and have found it very helpful for methodically exploring the space of hardware and software components. By representing an application's behavior as a set of metrics, where each metric is represented as a time series, temporal vertical profiling provides a way to reason about performance across system layers, regardless of their level of abstraction, and independent of their semantics. Temporal vertical profiling provides a methodology to explore a large space of metrics, hundreds of metrics even for small benchmarks, in a systematic way. Copyright © 2010 John Wiley & Sons, Ltd.

Automation systems become more and more complex, and their traditional hierarchical and centralized control may not be able to deal with this ever-increasing complexity satisfactorily. Decentralized approaches are considered promising, but they are not yet sufficiently understood for widespread industrial application. In particular, agent-based control has not yet achieved its potential, so that more research is still required. Our approach is based on the concept of an automation agent composed of a hardware (HW) component and a software (SW) component, where the HW component can be viewed as an embodiment of this SW component. These agents represent the parts of a flexible automation system. In particular, we propose that each such agent has an explicit symbolic representation of itself and of its relations to its environment. More precisely, this new agent architecture contains a reflective world model that includes a representation of this same agent and of its relations to its environment. In addition, the world model contains representations of situations and activities. We show that and how such a self-representation can be used for self-configuration, as well as monitoring, including failure detection in automation systems. The agent performs this self-configuration without any human intervention and just based on a brief specification of the HW configuration. The monitoring is based on automatically raised expectations for the system's behavior and allows failure detection without any specific failure detection code.

This study aimed to measure the impact of management information systems (MIS) across its dimensions (software components, human resources, hardware components, data, and networks) on the performance of employees at the Hope Center in Taiz. The study followed a descriptive-analytical approach and relied on a questionnaire as a data collection tool. The study population included all employees at the Hope Center, totaling 160 employees, at the levels of administrative director, department head, and technician. An electronic questionnaire was developed and distributed to members of the study population, and the number of respondents who constituted the study sample was 96 employees. The study found a statistically significant impact at a significance level of (α ≤ 0.05) of management information systems across its combined dimensions on the performance of employees at the Hope Center. It also found an impact at a significance level of (α ≤ 0.05) of the individual dimensions of information systems (software components, human resources, hardware components, data, and networks) on employee performance. The study recommended updating the software used at the center and training employees on how to use the systems.

Modern multi- and many-core systems are prone to concurrency-related bugs that surface only at system level. Detecting these bugs might require dealing with low-level hardware (HW) protocols and/or software (SW) inter-task interactions. Virtual platforms (VPs) offer a vehicle to conveniently debug HW/SW functionality, yet developers are mostly limited to manually breakpoint, step and interact with the system. To ease debugging during integration at system level, this paper introduces SWAT, an assertion-based debugging framework that checks and correlates system-wide interactions among HW and SW components. SWAT is used together with VPs to enable detecting HW/SW concurrency bugs with lower effort than traditional manual techniques. Our proposed approach is evaluated on two state-of-the-art platforms running real-world SW stacks.