Experiences from Debugging a PCIX-based RDMA-capable NIC

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

MOPS is a platform for surgical robotics research. It consists of hardware and software components for building surgical robot systems based on existing robot arms. The reference system presented in this paper has two robot arms, each with an adapter for mounting and actuating different types of surgical instruments. Additionally, the system has a high-resolution stereo camera and a simple operator console with haptic devices and foot pedals for teleoperating the manipulators. Software components are based on Robot Operating System (ROS) to keep them modular and reusable for different types of hardware. We evaluate the precision of our system for vision-based tasks and demonstrate its potential for surgical task automation. The mean end-to-end error, including that of the vision system, for a trajectory following task was 1.2mm / 0.3° for one manipulator and 2.7mm / 0.7° for the other. MOPS software and hardware components are made available under an open-source license to encourage collaboration and facilitate the advancement of surgical robotics research.

The attendance recording system is expected to provide data visualization to detect students who have attendance problems. The system consists of hardware and software components. The hardware components are data acquisition devices that can record student's attendance based on fingerprint identification. In addition to identifying users, the devices also perform registration and managing user identity data storage for identification purposes. This paper will discuss about the detail system design and implementation of the attendance recording devices, starts from an explanation of the general system architecture, then brief description about the subsystem for identification, registration, and data management on the device, and lastly the implementation and integration of overall system on the device.

The public transport system of New South Wales (NSW), Australia is impotent to receive 100% of the fare from light rail and buses due to the unavailability of a continuous real-time monitoring system. This scheme thereby seeks to help update the NSW public transport ticket collection system, with the aid of a counter that will be integrated into the public transportation within the Ticket Tapping Machine, to provide passenger count against the number of touches occurring at each stop; and thus, increasing the revenue. The product comprises of hardware and software components - the hardware system is located within the public transport while the software system incorporating a web portal is positioned for the authorities to have access to the real-time passenger data. At the hardware end, the ultrasonic sensors and the raspberry pi would detect the number of passengers on the transport and the LCD screen would display the number of passengers who had not tapped their smart card ticket. Additionally, the raspberry pi module used in the hardware component can denote the transportation location with the help of an in-built Wi-Fi component. With this designed technology, the authorities would be able to monitor and record the movements of the passenger in real-time system addressing the existing challenges faced by the NSW public transport authority, especially in the case of light rail and buses being used for free by certain passengers.

Modelling energy consumption of network transfers and virtual machine migration

Network interfaces for programmable NICs and multicore platforms

Modern systems are enormously complex; many applications today comprise millions of lines of code, make extensive use of software frameworks, and run on complex, multi‐tiered, run‐time systems. Understanding the performance of these applications is challenging because it depends on the interactions between the many software and the hardware components. This paper describes and evaluates an interactive and iterative methodology, temporal vertical profiling, for understanding the performance of applications. There are two key insights behind temporal vertical profiling. First, we need to collect and reason across information from multiple layers of the system before we can understand an application's performance. Second, application performance changes over time and thus we must consider the time‐varying behavior of the application instead of aggregate statistics. We have developed temporal vertical profiling from our own experience of analyzing performance anomalies and have found it very helpful for methodically exploring the space of hardware and software components. By representing an application's behavior as a set of metrics, where each metric is represented as a time series, temporal vertical profiling provides a way to reason about performance across system layers, regardless of their level of abstraction, and independent of their semantics. Temporal vertical profiling provides a methodology to explore a large space of metrics, hundreds of metrics even for small benchmarks, in a systematic way. Copyright © 2010 John Wiley & Sons, Ltd.

Automation systems become more and more complex, and their traditional hierarchical and centralized control may not be able to deal with this ever-increasing complexity satisfactorily. Decentralized approaches are considered promising, but they are not yet sufficiently understood for widespread industrial application. In particular, agent-based control has not yet achieved its potential, so that more research is still required. Our approach is based on the concept of an automation agent composed of a hardware (HW) component and a software (SW) component, where the HW component can be viewed as an embodiment of this SW component. These agents represent the parts of a flexible automation system. In particular, we propose that each such agent has an explicit symbolic representation of itself and of its relations to its environment. More precisely, this new agent architecture contains a reflective world model that includes a representation of this same agent and of its relations to its environment. In addition, the world model contains representations of situations and activities. We show that and how such a self-representation can be used for self-configuration, as well as monitoring, including failure detection in automation systems. The agent performs this self-configuration without any human intervention and just based on a brief specification of the HW configuration. The monitoring is based on automatically raised expectations for the system's behavior and allows failure detection without any specific failure detection code.

As the development of technology, the mobile phone world also has developed very quickly. Mobile communication and services, over emerging wireless technologies, provide anyone, anytime and anywhere access. Moreover, the intelligence is now often embedded into modern applications, such as surveillance and supervising systems. This work presents an intelligent and a pervasive supervising platform for information system (IS) security based on multi-agent systems (MAS) which detects and classifies malware events that occurs on software and hardware components and sends real time notification to smart phone users. The proposed platform is formed by two components: The first one consists of a Central Software Component (CSC); the supervisor application that manages devices and evaluates logs and alarms of the supervised components. The second one consists of an Embedded Software Component (ESC) on the Mobile Device (MD) with an ANDROID OS. In our platform, we have implemented agents on ESC using JADE-LEAP android, note that the ESC is targeted to smart phones and tablet that run the operating system Android, JADE API on CSC and the communication between these two components is performed using the Secure Socket Layer (SSL) protocol implemented using the JADE-S plug-in.

Commodity DRAM-based processing-using-memory (PuM) techniques that are supported by off-the-shelf DRAM chips present an opportunity for alleviating the data movement bottleneck at low cost. However, system integration of these techniques imposes non-trivial challenges that are yet to be solve d . Potential solutions to the integration challenges require appropriate tools to develop any necessary hardware and software components. Unfortunately, current proprietary computing systems, specialized DRAM-testing platforms, or system simulators do not provide the flexibility and/or the holistic system view that is necessary to properly evaluate and deal with the integration challenges of commodity DRAM-based PuM techniques. We design and develop Processing-in-DRAM (PiDRAM), the first flexible end-to-end framework that enables system integration studies and evaluation of real, commodity DRAM-based PuM techniques. PiDRAM provides software and hardware components to rapidly integrate PuM techniques across the whole system software and hardware stack. We implement PiDRAM on an FPGA-based RISC-V system. To demonstrate the flexibility and ease of use of PiDRAM, we implement and evaluate two state-of-the-art commodity DRAM-based PuM techniques: (i) in-DRAM copy and initialization (RowClone) and (ii) in-DRAM true random number generation (D-RaNGe) . We describe how we solve key integration challenges to make such techniques work and be effective on a real-system prototype, including memory allocation, alignment, and coherence. We observe that end-to-end RowClone speeds up bulk copy and initialization operations by 14.6× and 12.6×, respectively, over conventional CPU copy, even when coherence is supported with inefficient cache flush operations. Over PiDRAM’s extensible codebase, integrating both RowClone and D-RaNGe end-to-end on a real RISC-V system prototype takes only 388 lines of Verilog code and 643 lines of C++ code.

In the state-of-the-art hardware/software (HW/SW) co- design of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. Such an architectural specification ought to capture both hardware and software components and their interactions, and facilitate effective design exploitation of HW/SW trade-offs and scalable HW/SW co-verification. In this paper, we present the embedded architecture description language (EADL). It is based on a component model for embedded systems that unifies hardware and software components. EADL does not dictate execution and interface semantics of hardware and software components while supporting flexible platform-oriented semantics instantiation. EADL supports concise representation of embedded system architectures and also formulation of architectural patterns of embedded systems. Besides facilitating design reuse, architectural patterns also facilitate verification reuse via association of properly templates with these patterns. Effectiveness of EADL has been demonstrated by its successful application in integrating component-based co-design, co- simulation, co-verification, and system synthesis.

NaNet is a framework for the development of FPGA-based PCI Express (PCIe) Network Interface Cards (NICs) with real-time data transport architecture that can be effectively employed in TRIDAQ systems. Key features of the architecture are the flexibility in the configuration of the number and kind of the I/O channels, the hardware offloading of the network protocol stack, the stream processing capability, and the zero-copy CPU and GPU Remote Direct Memory Access (RDMA). Three NIC designs have been developed with the NaNet framework: NaNet-1 and NaNet-10 for the CERN NA62 low level trigger and NaNet3 for the KM3NeT-IT underwater neutrino telescope DAQ system. We will focus our description on the NaNet-10 design, as it is the most complete of the three in terms of capabilities and integrated IPs of the framework.

This study aimed to measure the impact of management information systems (MIS) across its dimensions (software components, human resources, hardware components, data, and networks) on the performance of employees at the Hope Center in Taiz. The study followed a descriptive-analytical approach and relied on a questionnaire as a data collection tool. The study population included all employees at the Hope Center, totaling 160 employees, at the levels of administrative director, department head, and technician. An electronic questionnaire was developed and distributed to members of the study population, and the number of respondents who constituted the study sample was 96 employees. The study found a statistically significant impact at a significance level of (α ≤ 0.05) of management information systems across its combined dimensions on the performance of employees at the Hope Center. It also found an impact at a significance level of (α ≤ 0.05) of the individual dimensions of information systems (software components, human resources, hardware components, data, and networks) on employee performance. The study recommended updating the software used at the center and training employees on how to use the systems.

Our investigation into architectural support for networking tasks began in late 1998, and it began with something of a coincidence. Fiuczynski was an active graduate student participant in the SPIN project at UW [2,3]. He had been writing a SPIN driver for a high-speed network interface card (NIC), and visited Crowley (at the time, a graduate student investigating the relationships between processor & memory architectures and desktop computer applications [4]) one afternoon to discuss the NIC's processor. Had either Fiuczynksi or Crowley been out of the office on that particular day, it is not clear that this collaboration would have emerged. As it happened, both were in the office that day and the NIC processor was very interesting: a dual-core MIPS-like processor built specifically for the NIC. In ensuing discussions, it became clear that-despite the simplicity of its instruction set and microarchitecture-the NIC processor was as a whole more interesting than the much larger and complex x86 processor of the host system. It was more interesting because, as a dual-core processor, it was different and in no way an incremental improvement upon the deeply pipelined CPUs that dominated computing at the time. (They still dominate PCs and servers, of course, but mobile, graphics and embedded chips represent a huge swath of relevant computing platforms today.) It represented evidence of a combination of commercial and technical justification for designing a new and different processor to handle networking tasks.

In multi-channel wireless mesh networks (WMNs), it is significantly important to achieve efficient channel utilization. The channel assignment problem, which investigates how to seek a proper mapping between available channels and network interface cards (NICs) on mesh routers (MRs), is attracting more and more attention from the research community. However, most proposed channel assignment approaches assume that NICs are evenly placed on the MRs, and its amount is also pre-determined. Due to the non-uniform distribution of WMN traffic, the equal interface placement will inevitably cause that the bottleneck MRs suffer from NIC shortage, and MRs with less load only have a low utilization of NICs. Hence, in order to improve network performance and reduce network cost, interface placement should be considered carefully in the process of planning a WMN. In this paper, we investigate the joint interface placement and channel assignment problem, i.e., how to appropriately place NICs on MRs and assign channels to them. We first formulate the problem as a mixed integer linear programming (MILP) model, which aims to minimize the total number of NICs while satisfying logical link, link bandwidth, link interference and traffic demand constraints. Then, we propose an MILP-based heuristic algorithm, using iterated local search to obtain sub-optimal solutions efficiently. Finally, we conduct simulation experiments to compare the heuristic solutions with the optimal solutions, and the results show that our proposed heuristic algorithm can achieve good sub-optimal solutions. Moreover, the simulation results also demonstrate that the algorithm can be well applied in large-scale WMNs where the optimal solutions cannot be obtained, and can perform well under different traffic demands.