Embedding of Hypercube into Fractal Cubic Network

A new and efficient technique is presented for modelling and simulation of interconnect networks which include multiconductor microstrip transmission lines (MMTL) with inhomogeneous cylindrical substrates. The potential and field distributions in the cross section of the MMTL are calculated by solving a set of series equations using Galerkin's method. The charge distribution on the conductors, maxwellian capacitance matrix per unit length, and the modal characteristic impedances of the MMTL are determined. Results obtained have been compared for various types of microstrip lines with those obtained in the literature; good agreement has been found.

Graph embedding has been known as a powerful tool for implementation of parallel algorithms and simulation of interconnection networks. In this paper, we introduce a technique to obtain a lower bound for the dilation of an embedding. Moreover, we give algorithms for embedding variants of hypercubes with dilation 2 proving that the lower bound obtained is sharp. Further, we compute the exact wirelength of embedding folded hypercubes and augmented cubes into hypercubes.

Neural networks have proved to be effective in solving a wide range of problems. As problems become more and more demanding, they require larger neural networks, and the time used for learning is consequently greater. Parallel implementations of learning algorithms are therefore vital for a useful application. Implementation, however, strongly depends on the features of the learning algorithm and the underlying hardware architecture. For this experimental work a dynamic problem was chosen which implicates the use of recurrent neural networks and a learning algorithm based on the paradigm of learning automata. Two parallel implementations of the algorithm were applied - one on a computing cluster using MPI and OpenMP libraries and one on a graphics processing unit using the CUDA library. The performance of both parallel implementations justifies the development of parallel algorithms.

Critical to any automated surveillance system is the recognition component. Since the inception of Pattern Recognition & Image processing, researchers across the globe continue to propose newer facial recognition algorithms. Each of these facial algorithms has its own pros and cons. A typical facial recognition algorithm consists of three steps namely: facial detection, feature extraction and recognition. In this paper we discuss serial and parallel implementation of four standard facial recognition algorithms namely, Principal Component Analysis (PCA), Linear Discriminant Analysis (LDA), Independent Component Analysis (ICA) and FISHER Face. Work presented in this paper consists of two sections. In section 1, we discuss serial and parallel implementation of the algorithms. Section 2, presents a comparative performance analysis of the above 4 algorithms. A major challenge in this effort is the ability to explore and exploit concurrency in existing facial recognition algorithms to improve performance. Based on the algorithms performance, we have made few suggestions regarding the suitability of each of these algorithms for different domains/applications. All algorithms are implemented using open source OPENCV and OPENMP libraries.

This paper describes the design and use of the interconnection network simulator (ICNS) framework. ICNS is a modular, object-oriented simulation system that has been developed to investigate performance issues in multiprocessor interconnection networks that exploit photonic technology in their design. We describe the ICNS infrastructure, present two distinct photonic interconnection networks that have been modeled using ICNS, and give performance results for each of these networks.

This paper presents a parallel algorithm for the simulation of large complex interconnect networks with frequency-dependent parameters. The equivalent transmission line model, which is suitable for time-domain simulation, is introduced for the modeling of dispersive interconnects. By means of the equivalent multi-port model, the interconnects are separated from other circuit elements, and thus makes the parallel simulation feasible. Based on the proposed technique, a program named FdSPICE is developed for parallel simulation of large interconnect networks. The accuracy and efficiency of FdSPICE are demonstrated by numerical examples.

Finite state automata are of fundamental importance in theory as well as applications in computer science. This dissertation presents several parallel algorithms for processing of them, including minimizing the number of states for a given finite state automaton, finding homing sequences for a given finite state automaton, converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. Implementation of some algorithms, as well as their experimental results, are also given. For minimization of deterministic finite automata, we present a parallel algorithm and discuss its implementation on a practical parallel machine using data parallel and message passing paradigms. Its time complexity on a p processor EREW PRAM $(p\\le n)$ for inputs of size n is $O({n\\log\\sp2n\\over p}+\\log n\\ \\log p)$ uniformly on almost all instances. The work done by our algorithm is thus within a factor of $O(\\log n)$ of the best known sequential algorithm. The space used by our algorithm is linear in the input size. The actual resource requirements of our implementations are consistent with these estimates. For finding homing sequences of deterministic finite automata, we present both deterministic and randomized algorithms. Two randomized algorithms of time complexity $O(log\\sp2n)$ are given. One of the randomized algorithms produces a homing sequence of length $O(n\\ log\\sp2n)$ for almost all DFA's with n states. The deterministic algorithm is based on a well known sequential algorithm. The implementation of the deterministic parallel algorithm shows that it can handle randomly generated instances with millions of states, and all DFA's with thousands of states using currently available parallel machines. Finally, we present an efficient parallel algorithm for converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. The resulting automaton is natural representation of a regular expression and has some important and practical uses in the document processing area. The time complexity of the algorithm is $O(\\log n)$ and the number of processors used is $O(n\\sp2).$

The use of conservative parallel simulation techniques to accelerate multistage interconnection network simulation is addressed. The conventional null-message approach to resolving the deadlock problem in conservative simulation may lead to a livelock if lookahead cannot be guaranteed. We propose a new deadlock/livelock free scheme using null messages, but without the presumed lookahead, to co-ordinate the parallel simulation. A flushing mechanism to address the combinatorial explosion of memory consumption due to such null messages is also discussed. Our analysis shows that the proposed flushing mechanism effectively reduces the memory consumption from exponential to linear. Different partitioning and transformation techniques are used to map the simulation program onto multiprocessor platforms. Both the empirical and analytical results show an exceptional phenomenon that a balanced simulation workload distribution may not necessarily translate into better run-time performance.

A Simple Parallel Algorithm for the Single-Source Shortest Path Problem on Planar Digraphs

We report on the parallel implementation of a multi-view image segmentation algorithm via segmenting the corresponding three-dimensional scene. The algorithm includes the reconstruction of a three-dimensional scene model in the form of a point cloud, and the segmentation of the resulting point cloud in three-dimensional space using the Hough space. The developed parallel algorithm was implemented on graphics processing units using CUDA technology. Experiments were performed to evaluate the speedup and efficiency of the proposed algorithm. The developed parallel program was tested on modelled scenes.

In this book chapter, the authors discuss some important communication issues to obtain a highly scalable computing system. They consider the CGM (Coarse-Grained Multicomputer) model, a realistic computing model to obtain scalable parallel algorithms. The communication cost is modeled by the number of communication rounds and the objective is to design algorithms that require the minimum number of communication rounds. They discuss some important issues and make considerations of practical importance, based on our previous experience in the design and implementation of parallel algorithms. The first issue is the amount of data transmitted in a communication round. For a practical implementation to be successful they should attempt to minimize this amount, even when it is already within the limit allowed by the CGM model. The second issue concerns the trade-off between the number of communication rounds which the CGM attempts to minimize and the overall communication time taken in the communication rounds. Sometimes a larger number of communication rounds may actually reduce the total amount of data transmitted in the communications rounds. These two issues have guided us to present efficient parallel algorithms for the string similarity problem, used as an illustration.

Principal component analysis (PCA) is a key statistical technique for multivariate data analysis. For large data sets, the common approach to PCA computation is based on the standard NIPALS-PCA algorithm, which unfortunately suffers from loss of orthogonality, and therefore its applicability is usually limited to the estimation of the first few components. Here we present an algorithm based on Gram-Schmidt orthogonalization (called GS-PCA), which eliminates this shortcoming of NIPALS-PCA. Also, we discuss the GPU (Graphics Processing Unit) parallel implementation of both NIPALS-PCA and GS-PCA algorithms. The numerical results show that the GPU parallel optimized versions, based on CUBLAS (NVIDIA), are substantially faster (up to 12 times) than the CPU optimized versions based on CBLAS (GNU Scientific Library).

Ray tracing is a well known technique to generate life-like images. Unfortunately, ray tracing complex scenes can require large amounts of CPU time and memory storage. Distributed memory parallel computers with large memory capacities and high processing speeds are ideal candidates to perform ray tracing. However, the computational cost of rendering pixels and patterns of data access cannot be predicted until runtime. To parallelize such an application efficiently on distributed memory parallel computers, the issues of database distribution, dynamic data management and dynamic load balancing must be addressed. In this paper, we present a parallel implementation of a ray tracing algorithm on the Intel Delta parallel computer. In our database distribution, a small fraction of database is duplicated on each processor, while the remaining part is evenly distributed among groups of processors. In the system, there are multiple copies of the entire database in the memory of groups of processors. Dynamic data management is acheived by an ALRU cache scheme which can exploit image coherence to reduce data movements in ray tracing consecutive pixels. We balance load among processors by distributing subimages to processors in a global fashion based on previous workload requests. The success of our implementation depends crucially on a number of parameters which are experimentally evaluated. © 1997 John Wiley & Sons, Ltd.

Physiologic trend detection and artifact rejection: a parallel implementation of a multi-state Kalman filtering algorithm

In this paper we show the difficulties encountered when performing full system simulation of a distributed memory parallel system. To illustrate the problem, we have chosen a workbench that evaluates the impact on application performance of some simple congestion-control mechanism that can be implemented in the interconnection network. Applications of choice are some of those included in the NAS parallel benchmarks. Running a full-system, execution-driven simulation that combines Simics with an interconnection network simulator, we observe some unexpected, negative interactions of overlapping congestion control techniques implemented at the network level and at the host level. Each MPI implementation uses a different protocol stack, and some of them work without TCP. We compare and contrast results obtained with MPICH, LA-MPI and LAM