Energy and Space Efficient Parallel Adder Using Molecular Memristors.

Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing - particularly in MAJ-based realizations - and the use of techniques proposed for optimization.

Memristive technology is the fast emerging alternative to the traditional computing architectures because of its In-Memory-Computation (IMC) capability and low area footprint. Subtraction is a basic arithmetic operation in microprocessors and digital signal processing applications. An IMPLY-based one-bit subtractor is proposed with five memristors and requires nineteen computational steps. Further, this paper presents two multi-bit subtractor designs. One is a serial approach, which has less number of memristors, while the second design is a parallel approach with less number of computational steps. In particular, a 32-bit serial subtractor takes 67 memristors and parallel subtractor takes 174 steps to compute the output. A 32-bit subtractor designed in parallel approach has a better Figure-of-Merit with a 29% improvement compared to the best existing design.

An effective matrix operation is critical to process 2-D DCT. This paper presents a hierarchically controlled SIMD array (HCSA) well suited to matrix computations, in which a conventional 2-D torus is enhanced with the hierarchical organization of control units and the global data buses running across the rows and columns. The distinguished features of the HCSA are the diagonally indexed concurrent broadcast and the efficient data exchanges among PEs through either row or column broadcast. Therefore, the HCSA can provide significant improvement on computation steps of DCT. For the performance evaluation, an algorithmic mapping method is used and the number of computation steps is analytically compared with semisystolic architecture.KeywordsDiscrete Cosine TransformSystolic ArrayDiscrete Cosine Transform CoefficientInverse Discrete Cosine TransformHost ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Memristive devices offer non-volatile storage capabilities, along with in-memory computation capabilities. Large scale passive crossbar arrays can be enabled by avoiding parasitic paths by means of a select device in series with a resistive switching device (1S1R). In this work, we utilize 1S1R Resistive RAM (ReRAM) arrays for realization of logic-in-memory operations, where each device is capable of performing the Boolean Majority operation with an input inverted. In contrast to the prior works, for the first time, we enable memristor-aided n-input OR operation in the same memristive array - some memristors initialized with data act as input and an additional memristor acts as output. By extending the reach of the underlying devices in terms of logic primitives, we boost the optimization of logical depth and device count. This improvement is demonstrated through a representative case study. This paves the way for new and improved memristive crossbar designs, compared to the state-of-the-art Majority only or NOR only memristive approaches.

In complementary metal–oxide–semiconductor (CMOS)‐based von Neumann architectures, the intrinsic power and speed inefficiencies are worsened by the drastic increase in information with big data. With the potential to store numerous values in I–V pinched hysteresis, memristors (memory resistors) have emerged as alternatives to existing CMOS‐based computing systems. Herein, four types of memristive devices, namely, resistive switching, phase‐change, spintronics, and ferroelectric tunnel junction memristors, are explored. The application of these devices to a crossbar array (CBA), which is a novel concept of integrated architecture, is a step toward the realization of ultradense electronics. Exploiting the fascinating capabilities of memristive devices, computing systems can be developed with novel computing paradigms, in which large amounts of data can be stored and processed within CBAs. Looking further ahead, the ways in which memristors could be incorporated in neuromorphic computing systems along with various artificial intelligence algorithms are established. Finally, perspectives and challenges that memristor technology should address to provide excellent alternatives to existing computing systems are discussed. The infinite potential of memristors is the key to unlock new computing paradigms, which pave the way for next‐generation computing systems.

Many breakthroughs in technologies are closely associated with the deep understanding and development of new material platforms. As the main material used in microelectronics, Si also plays a leading role in the development of integrated photonics. The indirect bandgap, absence of χ(2) nonlinearity and the parasitic nonlinear absorptions at the telecom band of Si imposed technological bottlenecks for further improving the performances and expanding the functionalities of Si microcavities in which the circulating light intensity is dramatically amplified. The past two decades have witnessed the burgeoning of the novel material platforms that are compatible with the complementary metal-oxide-semiconductor (COMS) process. In particular, the unprecedented optical properties of the emerging materials in the thin film form have resulted in revolutionary progress in microcavity photonics. In this review article, we summarize the recently developed material platforms for integrated photonics with the focus on chip-scale microcavity devices. The material characteristics, fabrication processes and device applications have been thoroughly discussed for the most widely used new material platforms. We also discuss open challenges and opportunities in microcavity photonics, such as heterogeneous integrated devices, and provide an outlook for the future development of integrated microcavities.

Techniques for reasoning about extensional properties of functional programs are well understood, but methods for analysing the underlying intensional or operational properties have been much neglected. This paper begins with the development of a simple but useful calculus for time analysis of non-strict functional programs with lazy lists. One limitation of this basic calculus is that the ordinary equational reasoning on functional programs is not valid. In order to buy back some of these equational properties we develop a non-standard operational equivalence relation called cost equivalence. by considering the number of computation steps as an ‘observable’ component of the evaluation process. We define this relation by analogy with Park's definition of bisimulation in CCS. This formulation allows us to show that cost equivalence is a contextual congruence (and thus is substitutive with respect to the basic calculus) and provides useful proof techniques for establishing cost-equivalence laws. It is shown that basic evaluation time can be derived by demonstrating a certain form of cost equivalence, and we give an axiomatization of cost equivalence which is complete with respect to this application. This shows that cost equivalence subsumes the basic calculus. Finally we show how a new operational interpretation of evaluation demands can be used to provide a smooth interface between this time analysis and more compositional approaches, retaining the advantages of both.

In the online checkpointing problem, the task is to continuously maintain a set of k checkpoints that allow to rewind an ongoing computation faster than by a full restart. The only operation allowed is to replace an old checkpoint by the current state. Our aim are checkpoint placement strategies that minimize rewinding cost, i.e., such that at all times T when requested to rewind to some time t≤T the number of computation steps that need to be redone to get to t from a checkpoint before t is as small as possible. In particular, we want that the closest checkpoint earlier than t is not further away from t than qk times the ideal distance T / (k+1), where qk is a small constant. Improving over earlier work showing 1+1/k≤qk≤2, we show that qk can be chosen asymptotically less than 2. We present algorithms with asymptotic discrepancy qk≤1.59+o(1) valid for all k and qk≤ln (4)+o(1)≤1.39+o(1) valid for k being a power of two. Experiments indicate the uniform bound pk≤1.7 for all k. For small k, we show how to use a linear programming approach to compute good checkpointing algorithms. This gives discrepancies of less than 1.55 for all k<60. We prove the first lower bound that is asymptotically more than one, namely qk≥1.30−o(1). We also show that optimal algorithms (yielding the infimum discrepancy) exist for all k.

An extension of a result by Grigoryev is used to derive a lower bound on the space-time product required for integer multiplication when realized by straight-line algorithms. If S is the number of temporary storage locations used by a straight-line algorithm on a random-access machine and T is the number of computation steps, then we show that (S+1)T ⩾ Ω(n2) for binary integer multiplication when the basis for the straight-line algorithm is a set of Boolean functions.KeywordsBoolean FunctionInteger MultiplicationCombinatorial ArgumentPebble GameOblivious AlgorithmThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

High density 3D memory architecture based on the resistive switching effect

In recent years, molecular perovskite energetic materials have attracted more attention because of their simple synthesis processes, high thermal stabilities, excellent performances, and great significance as a design platform for energetic materials. To explore the possibility of the application of molecular perovskite energetic materials in heat-resistant explosives, four silver(I)-based molecular perovskite energetic compounds, (H2A)[Ag(ClO4)3], where H2A = piperazine-1,4-diium (H2pz2+) for PAP-5, 1-methyl-piperazine-1,4-diium (H2mpz2+) for PAP-M5, homopiperazine-1,4-diium (H2hpz2+) for PAP-H5, and 1,4-diazabicyclo[2.2.2]octane-1,4-diium (H2dabco2+) for DAP-5, were synthesized by a one-pot self-assembly strategy and structurally characterized. The single-crystal structures indicated that PAP-5, PAP-M5, and DAP-5 possess cubic perovskite structures while PAP-H5 possesses a hexagonal perovskite structure. Differential thermal analyses showed that their onset decomposition temperatures are >308.3 °C. For PAP-5 and DAP-5, they have not only exceptional calculated detonation parameters (D values of 8.961 and 8.534 km s-1 and P values of 42.4 and 37.9 GPa, respectively) but also the proper mechanical sensitivity (impact sensitivities of ≤10 J for PAP-5 and 3 J for DAP-5 and friction sensitivities of ≤5N for both PAP-5 and DAP-5) and thus are of interest as potential heat-resistant primary explosive components.

The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated under different bias schemes and transient simulations of write operations were performed under various operating conditions. The variance of the switching time and problematic behaviors was investigated. The floating bias scheme was compared with the 1/2 bias scheme, and simulation results revealed that write errors may be induced in the floating bias scheme by abnormal glitches occurring when the parasitic capacitance becomes large.

Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge. The brute-force and exact maximum likelihood (ML) decoder, solved on conventional classical digital hardware to decode MIMO symbols, has exponential time complexity. Approximate classical solvers implemented on the same hardware have polynomial time complexity at the best. In this article, we design an alternative ring-oscillator-based coupled oscillator array (also known as oscillatory neural network (ONN)) to act as an oscillator Ising machine (OIM) and heuristically solve the ML-based MIMO detection problem. Complementary metal oxide semiconductor (CMOS) technology is used to design the ring oscillators, and ferroelectric field effect transistor (FeFET) technology is chosen as the non-volatile memory (NVM) coupling element (X) between the oscillators in this CMOS + X OIM design. For this purpose, we experimentally report high linear range of conductance variation (1 µS to 60 µS) with programming voltage pulses in a HfO 2 -based FeFET device fabricated at 28 nm high-K/ metal gate (HKMG) CMOS technology node. We incorporate the conductance modulation characteristic in SPICE simulation of the ring oscillators connected in an all-to-all fashion through a crossbar array of these FeFET devices. We show that the above range of conductance variation of FeFET is suitable to obtain best OIM performance, thereby making FeFET a suitable NVM device for this application. Our SPICE simulations show that there is no significant performance drop for symbol detection up to MIMO array sizes of 90 transmitting and 90 receiving antennas. Our simulations, combined with analytical treatment using Kuramoto model of oscillators, predict that this designed classical analog OIM, if implemented experimentally, will offer logarithmic scaling of computation time with MIMO size, thereby offering huge improvement (in terms of computation speed) over exact and approximate classical solvers run on conventional digital hardware.