Space-time tradeoffs for oblivious integer multiplication

Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing - particularly in MAJ-based realizations - and the use of techniques proposed for optimization.

An effective matrix operation is critical to process 2-D DCT. This paper presents a hierarchically controlled SIMD array (HCSA) well suited to matrix computations, in which a conventional 2-D torus is enhanced with the hierarchical organization of control units and the global data buses running across the rows and columns. The distinguished features of the HCSA are the diagonally indexed concurrent broadcast and the efficient data exchanges among PEs through either row or column broadcast. Therefore, the HCSA can provide significant improvement on computation steps of DCT. For the performance evaluation, an algorithmic mapping method is used and the number of computation steps is analytically compared with semisystolic architecture.KeywordsDiscrete Cosine TransformSystolic ArrayDiscrete Cosine Transform CoefficientInverse Discrete Cosine TransformHost ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Memristive technology is the fast emerging alternative to the traditional computing architectures because of its In-Memory-Computation (IMC) capability and low area footprint. Subtraction is a basic arithmetic operation in microprocessors and digital signal processing applications. An IMPLY-based one-bit subtractor is proposed with five memristors and requires nineteen computational steps. Further, this paper presents two multi-bit subtractor designs. One is a serial approach, which has less number of memristors, while the second design is a parallel approach with less number of computational steps. In particular, a 32-bit serial subtractor takes 67 memristors and parallel subtractor takes 174 steps to compute the output. A 32-bit subtractor designed in parallel approach has a better Figure-of-Merit with a 29% improvement compared to the best existing design.

A breakthrough in in-memory computing technologies hinges on the development of appropriate material platforms that can overcome their existing limitations, such as larger than optimal footprint and multiple serial computational steps, with potential accumulation of errors. Using a molecular switching element with multiple non-monotonic and deterministic transitions, the device count and the number of computational steps can be substantially reduced. With molecular materials, however, the realization of a reliable and robust platform isan unattained goal for decades. Here, crossbar arrays with up to 64 molecular memristors are fabricated to experimentally demonstrate 8-bit serial and 4-bit parallel addersthat operate for thousands of measurement cycles with an estimated error probability of 10-16 . For performance benchmarking, a 32-bit parallel adder is designed and simulated with 268million inputs including contributions from the peripheral circuitry showing a 47× higher energy efficiency, 93× faster operation, and 9% of the footprint, leading to 4390 times improved energy-delay product compared to a special purpose complementary metal-oxide-semiconductor (CMOS)-based multicore adder.

Techniques for reasoning about extensional properties of functional programs are well understood, but methods for analysing the underlying intensional or operational properties have been much neglected. This paper begins with the development of a simple but useful calculus for time analysis of non-strict functional programs with lazy lists. One limitation of this basic calculus is that the ordinary equational reasoning on functional programs is not valid. In order to buy back some of these equational properties we develop a non-standard operational equivalence relation called cost equivalence. by considering the number of computation steps as an ‘observable’ component of the evaluation process. We define this relation by analogy with Park's definition of bisimulation in CCS. This formulation allows us to show that cost equivalence is a contextual congruence (and thus is substitutive with respect to the basic calculus) and provides useful proof techniques for establishing cost-equivalence laws. It is shown that basic evaluation time can be derived by demonstrating a certain form of cost equivalence, and we give an axiomatization of cost equivalence which is complete with respect to this application. This shows that cost equivalence subsumes the basic calculus. Finally we show how a new operational interpretation of evaluation demands can be used to provide a smooth interface between this time analysis and more compositional approaches, retaining the advantages of both.

In the online checkpointing problem, the task is to continuously maintain a set of k checkpoints that allow to rewind an ongoing computation faster than by a full restart. The only operation allowed is to replace an old checkpoint by the current state. Our aim are checkpoint placement strategies that minimize rewinding cost, i.e., such that at all times T when requested to rewind to some time t≤T the number of computation steps that need to be redone to get to t from a checkpoint before t is as small as possible. In particular, we want that the closest checkpoint earlier than t is not further away from t than qk times the ideal distance T / (k+1), where qk is a small constant. Improving over earlier work showing 1+1/k≤qk≤2, we show that qk can be chosen asymptotically less than 2. We present algorithms with asymptotic discrepancy qk≤1.59+o(1) valid for all k and qk≤ln (4)+o(1)≤1.39+o(1) valid for k being a power of two. Experiments indicate the uniform bound pk≤1.7 for all k. For small k, we show how to use a linear programming approach to compute good checkpointing algorithms. This gives discrepancies of less than 1.55 for all k<60. We prove the first lower bound that is asymptotically more than one, namely qk≥1.30−o(1). We also show that optimal algorithms (yielding the infimum discrepancy) exist for all k.

In this paper, we propose a temporal decimal multiplier design that reduces the area and pin count compared to an equivalent binary multiplier. In this design, we have efficiently embedded time-to-decimal conversion inside the logic, which mitigates the need for external conversion circuits. Also, our design mitigates a drawback of temporal logic that typically requires ‘n’ time delays to represent ‘n’ numerical values, which results in longer latency for large values of ‘n’. By representing numbers as parallel temporal values where each value represents a different digit (0–9) of the number, we reduce the maximum delay needed to represent the product to only 9 delay (clock) cycles for any multiplication outcome. We show performance and area benefits for different temporal multiplier designs with fully-laid out, tapeout-ready design implemented in MITLL's SFQ5ee process. Compared to a 4-bit binary multiplier, our temporal decimal multiplier reduces the pin count by approximately 3× and the area by 40%. Finally, we evaluate our proposed temporal multiplier against conventional binary multipliers when configured for DSP and machine learning algorithms.

In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

In this paper we deal with 3-way split formulas for binary field multiplication with five recursive multiplications of smaller sizes. We first recall the formula proposed by Bernstein at CRYPTO 2009 and derive the complexity of a parallel multiplier based on this formula. We then propose a new set of 3-way split formulas with five recursive multiplications based on field extension. We evaluate their complexities and provide a comparison.KeywordsCritical PathPolynomial MultiplicationElliptic Curve CryptographyInductive RelationArithmetic ComplexityThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Comparison between two policy strategies for scheduling trucks in a biomass logistic system

We consider learning on multilayer neural nets with piecewise polynomial activation functions and a fixed number k of numerical inputs. We exhibit arbitrarily large network architectures for which efficient and provably successful learning algorithms exist in the rather realistic refinement of Valiant's model for probably approximately correct learning ("PAC learning") where no a priori assumptions are required about the "target function" (agnostic learning), arbitrary noise is permitted in the training sample, and the target outputs as well as the network outputs may be arbitrary reals. The number of computation steps of the learning algorithm LEARN that we construct is bounded by a polynomial in the bit-length n of the fixed number of input variables, in the bound s for the allowed bit-length of weights, in 1/ε, where ε is some arbitrary given bound for the true error of the neural net after training, and in 1/δ where δ is some arbitrary given bound for the probability that the learning algorithm fails for a randomly drawn training sample. However, the computation time of LEARN is exponential in the number of weights of the considered network architecture, and therefore only of interest for neural nets of small size. This article provides details to the previously published extended abstract (Maass 1994).

An eMathTeacher [16] is an eLearning on-line self-assessment tool that helps users to active learning math concepts and algorithms by themselves, correcting their mistakes and providing them with c...

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. The method uses a tunable quadrature sigma-delta modulator to re-quantise a real- or complex-valued input stream to a reduced precision, so removing the requirement for a full multiplier in the filter hardware. This makes the technique very attractive for implementation using FPGAs. The re-quantisation process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantisation noise to the spectral region to be rejected by the filter. The filter architecture described and its implementation using Xilinx FPGAs is presented.KeywordsField Programmable Gate ArrayFinite Impulse ResponseFilter CoefficientFinite Impulse Response FilterFeedback PathThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

More than 50% of the cost to load, haul, and deliver a weekly supply of herbaceous biomass from temporary storage locations near the production fields to a bioprocessing plant (50 Mg/h average capacity, 24/7 operation) is from truck ownership cost. The management policy that a bioprocessing plant uses to schedule trucks determines the maximum number of trucks required and thereby, the total cost for the logistics system. Two different management policies, one based on travel time (Policy 1) and another based on the assignment of trucks to given sectors of the surrounding production base (Policy 2) was used to develop truck schedules. The logistic system was modeled as a discrete event simulation model, and the schedule was validated.

Cloud and parallel computing are fundamental components in the processing of large data sets. Deployments of distributed computers require network infrastructure that is fast, efficient, and secure. Software Defined Networking (SDN) separates the forwarding of network data by switches (data plane) from the setting and managing of network policies (control plane). While this separation provides flexibility for setting network policies affecting the establishment of network flows in the data plane, it provides little to no fault tolerance for failures, either benign or caused by corrupted/malicious applications. Such failures can cause network flows to be incorrectly routed through the network or stop such flows altogether. Without protection against faults, cloud network providers using SDN run the risk of inefficient allocation of network resources or even data loss. Furthermore, the asynchronous nature existing protocols for SDN does not provide a mechanism for consistency in network policy updates across multiple switches.In addition, cloud and parallel applications require an efficient means for accessing local system data (input data sets, temporary storage locations, etc.). While in many cases it may be possible for a process to access this data by making calls directly to a file system (FS) kernel driver, this is not always possible (e.g. when using experimental distributed FSs where the needed libraries for accessing the FS only exist in user space).This dissertation provides a design for fault tolerance of SDN and infrastructure for advancing the performance of user space FSs. It is divided into three main parts. The first part describes a fault tolerant, distributed SDN control plane framework. The second part expands upon the fault tolerant approach to SDN control plane by providing a practical means for dynamic control plane membership as well as providing a simple mechanism for controller authentication through threshold signatures. The third part describes an efficient framework for user space FS access.This research makes three contributions. First, the design, specification, implementation, and evaluation of a method for fault tolerant SDN control plane that is inter-operable with existing control plane applications involving minimal instrumentation of the data plane runtime. Second, the design, specification, implementation and evaluation of a mechanism for dynamic SDN control plane membership that all ensure consistency of network policy updates and minimizes switch overhead through the use of distributed key generation and threshold signatures. Third, the design, specification, implementation, and evaluation of a user space FS access framework that is correct to the Portable Operating System Interface (POSIX) specification with significantly better performance over existing user space access methods, while requiring no implementation changes for application programmers.