Energy-Efficient Neuromorphic Computing with Spiking Neural Networks on Edge Devices: A Dynamic Programming Approach

Efficiently solving combinatorial optimization problems (COPs) such as Max-Cut is challenging because the resources required increase exponentially with the problem size. This study proposes a hardware-friendly method for solving the Max-Cut problem by implementing a spiking neural network (SNN)-based Boltzmann machine (BM) in neuromorphic hardware systems. To implement the hardware-oriented version of the spiking Boltzmann machine (sBM), the stochastic dynamics of leaky integrate-and-fire (LIF) neurons with random walk noise are analyzed, and an innovative algorithm based on overlapping time windows is proposed. The simulation results demonstrate the effective convergence and high accuracy of the proposed method for large-scale Max-Cut problems. The proposed method is validated through successful hardware implementation on a 6-transistor/2-resistor (6T2R) neuromorphic chip with phase change memory (PCM) synapses. In addition, as an expansion of the algorithm, several annealing techniques and bias split methods are proposed to improve convergence, along with circuit design ideas for efficient evaluation of sampling convergence using cell arrays and spiking systems. Overall, the results of the proposed methods demonstrate the potential of energy-efficient and hardware-implementable approaches using SNNs to solve COPs. To the best of the author's knowledge, this is the first study to solve the Max-Cut problem using an SNN neuromorphic hardware chip.

For most, if not all, AI-accelerated hardware, communication with the agent is expensive and heavily bottlenecks the hardware performance. This omnipresent hardware restriction is also found in neuromorphic computing: a novel style of computing that involves deploying spiking neural networks to specialized hardware to achieve low size, weight, and power (SWaP) compute. In neuromorphic computing, spike trains, times, and values are used to communicate information to, from, and within the spiking neural network. Input data, in order to be presented to a spiking neural network, must first be encoded as spikes. After processing the data, spikes are communicated by the network that represent some classification or decision that must be processed by decoder logic. In this paper, we first present principles for interconverting between spike trains, times, and values using custom-designed spiking subnetworks. Specifically, we present seven networks that encompass the 15 conversion scenarios between these encodings. We then perform three case studies where we either custom design a novel network or augment existing neural networks with these conversion subnetworks to vastly improve their communication performance with the outside world. We employ a classic space vs. time tradeoff by pushing spike data encoding and decoding techniques into the network mesh (increasing space) in order to minimize intra- and extranetwork communication time. This results in a classification inference speedup of 23× and a control inference speedup of 4.3× on field-programmable gate array hardware.

In recent years, spiking neural networks (SNNs), which originated from the theoretical basis of neuroscience, have attracted neuromorphic computing and brain-like computing due to their advantages, such as neural dynamics and coding mechanism, which are similar to biological neurons. SNNs have become one of the mainstream frameworks in the field of brain-like computing. However, most of the Leaky Integrate-and-Fire (LIF) neuron models currently used by SNNs based on direct training of backpropagation (BP) do not consider the changes in the recurrent connections and the dynamic strength of neuron connections over time. This study presented the LIF neuron model with recurrent connections and a method for dynamically changing the presynaptic currents. Recurrent LIF neurons have an additional cyclic connection compared with classic LIF neurons. Their postsynaptic current stimulates a change in membrane potential at the next time point. Their dynamics were more similar to the activities of biological neurons. We also proposed an efficient and flexible BP training method for recurrent LIF neurons. On the basis of the above methods, we proposed the recurrent SNN with dynamic presynaptic currents based on backpropagation (RDS-BP). We test the proposed RDS-BP on three image data sets (MNIST, Fashion-MNIST and CIFAR-10) and two text data sets (IMDB and TREC). The results showed that the performance of RDS-BP not only exceeded the naive SNN models based on BP but also exceeded the SNN methods proposed in previous studies in recent years, which had excellent performance in previous experiments. Our work provides a new LIF neuron model with a recurrent connection and dynamic presynaptic current and a BP training arrangement for the proposed neuron, which could merit developments with neuromorphic and brain-like computing.

Neuromorphic computing is a promising technology for future machine learning research, which is envisioned to provide lower power consumption, fault tolerance, and massive parallelism. However, the neuromorphic network, i.e., spike neural network (SNN), suffers from a broader range of its application compared with artificial neural networks (ANN). In this work, we propose a stochastic computation SC-based hybrid ANN and SNN scheme, which supports both ANN and SNN computation in SC domain. The ANN computation is converted to SC, which is implemented with simple logic gates. Moreover, we propose a new two-stage stochastic computation that is compatible with the sequence computation style of SNN. Consequently, the logic resource for the hybrid SNN and ANN can be shared. Compared to the state-of-the-art hybrid scheme, the proposed SC-based ANN and SNN exhibit much lower hardware costs and higher hardware efficiency.

Neuromorphic computers emulate the human brain while being extremely power efficient for computing tasks. In fact, they are poised to be critical for energy-efficient computing in the future. Neuromorphic computers are primarily used in spiking neural network–based machine learning applications. However, they are known to be Turing-complete, and in theory can perform all general-purpose computation. One of the biggest bottlenecks in realizing general-purpose computations on neuromorphic computers today is the inability to efficiently encode data on the neuromorphic computers. To fully realize the potential of neuromorphic computers for energy-efficient general-purpose computing, efficient mechanisms must be devised for encoding numbers. Current encoding mechanisms (e.g., binning, rate-based encoding, and time-based encoding) have limited applicability and are not suited for general-purpose computation. In this paper, we present the virtual neuron abstraction as a mechanism for encoding and adding integers and rational numbers by using spiking neural network primitives. We evaluate the performance of the virtual neuron on physical and simulated neuromorphic hardware. We estimate that the virtual neuron could perform an addition operation using just 23 nJ of energy on average with a mixed-signal, memristor-based neuromorphic processor. We also demonstrate the utility of the virtual neuron by using it in some of the μ-recursive functions, which are the building blocks of general-purpose computation.

Spiking Neural Networks (SNNs) aim at providing energy-efficient learning capabilities when implemented on neuromorphic chips with event-based Dynamic Vision Sensors (DVS). This paper studies the robustness of SNNs against adversarial attacks on such DVS-based systems, and proposes R-SNN, a novel methodology for robustifying SNNs through efficient DVS-noise filtering. We are the first to generate adversarial attacks on DVS signals (i.e., frames of events in the spatio-temporal domain) and to apply noise filters for DVS sensors in the quest for defending against adversarial attacks. Our results show that the noise filters effectively prevent the SNNs from being fooled. The SNNs in our experiments provide more than 90% accuracy on the DVS-Gesture and NMNIST datasets under different adversarial threat models.

Spiking Neural Networks (SNNs) are brain-inspired computational networks that promise an efficient solution for real-life applications such as audio processing and pattern recognition. An SNN is a complex network of neurons interconnected with synapses, whose spike times and synaptic strength is essential for information processing. SNNs consume low power and perform computations in parallel, making them attractive for hardware implementation of applications in neuromorphic engineering. For hardware implementation of SNNs, we need devices that mimic the behavior of neurons and synapses as well as their computational models to build and characterize large-scale SNNs. Earlier, a Pr <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> Ca <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> MnO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> (PCMO) material based Resistive-RAM (RRAM) has been used to experimentally demonstrate an Integrate and Fire (IF) Neuron and Izhikevich Neuron. Here, we present an experimentally validated Verilog-A model of PCMO RRAM, which behaves like a neuron. The model captures the conductance change of the RRAM for different applied voltages and can mimic an IF Neuron and an Izhikevich Neuron. The model enables the design of large-scale SNNs and studies their behavior in a simulation domain.

Spiking neural network (SNN) has drawn research interests as it mimics dynamic activities of human brain and has the potential to perform real-time cognitive tasks. However, latency, throughput and flexibility of existing hardware implemented SNNs are limited. The conventional rate coding is inefficient in terms of accuracy and latency. Oversimplified SNN models adopted by neuromorphic hardware discard characteristics such as neuron dynamics and filter effects etc., which are critical for neural information processing. Recent research advancements show that the potential of SNN can be better utilized by moving beyond rate-based model and considering temporal information embedded in the spike sequences. However, these works employ complex biologically realistic SNN models, posing challenges to hardware complexity. Furthermore, most existing neuromorphic hardware are developed for specific SNN models, or aiming at replicating biological behaviors. There is a lack of general methodology for SNN design optimization. Novel hardware architecture and systematic optimization techniques are required for efficient FPGA implementation and support flexible SNN models. To address above issues, in this work we proposed a holistic optimization framework for encoder, model, and architecture design of FPGA based neuromorphic hardware. We present an efficient neural coding scheme and training algorithm, which can optimize encoder parameters to enable fast inference. A flexible and hardware-friendly model is proposed, in which SNNs are represented as a network of Infinite Impulse Response (IIR) filters. Finally, an end-to-end framework is developed to optimize and deploy FPGA implementation. Experimental results show our work achieves state-of-the-art accuracy in various classification tasks, and outperforms various platforms including CPU, GPU and dedicated neuromorphic processors in terms of latency and throughput.

A spiking neural network (SNN) is a bottom-up tool used to describe information processing in brain microcircuits. It is becoming a crucial neuromorphic computational model. Spike-timing-dependent plasticity (STDP) is an unsupervised brain-like learning rule implemented in many SNNs and neuromorphic chips. However, a significant performance gap exists between ideal model simulation and neuromorphic implementation. The performance of STDP learning in neuromorphic chips deteriorates because the resolution of synaptic efficacy in such chips is generally restricted to 6 bits or less, whereas simulations employ the entire 64-bit floating-point precision available on digital computers. Previously, we introduced a bio-inspired learning rule named adaptive STDP and demonstrated via numerical simulation that adaptive STDP (using only 4-bit fixed-point synaptic efficacy) performs similarly to STDP learning (using 64-bit floating-point precision) in a noisy spike pattern detection model. Herein, we present the experimental results demonstrating the performance of adaptive STDP learning. To the best of our knowledge, this is the first study that demonstrates unsupervised noisy spatiotemporal spike pattern detection to perform well and maintain the simulation performance on a mixed-signal CMOS neuromorphic chip with low-resolution synaptic efficacy. The chip was designed in Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS technology node and comprises a soma circuit and 256 synapse circuits along with their learning circuitry.

In recent years, neuromorphic computing has become an important emerging research area. Neuromorphic computing takes advantage of computer architectures and sensors whose design and functionality are inspired by the brain. There has been rapid progress in computational theory, spiking neurons, learning algorithms, signal processing, circuit design and implementation, which have shown appealing computational advantages over conventional solutions [1]. The low size, weight, and power of these hardware architectures shows great potential for embedded cognitive systems [2].

With recent advances in learning algorithms, recurrent networks of spiking neurons are achieving performance that is competitive with vanilla recurrent neural networks. However, these algorithms are limited to small networks of simple spiking neurons and modest-length temporal sequences, as they impose high memory requirements, have difficulty training complex neuron models and are incompatible with online learning. Here, we show how the recently developed Forward-Propagation Through Time (FPTT) learning combined with novel liquid time-constant spiking neurons resolves these limitations. Applying FPTT to networks of such complex spiking neurons, we demonstrate online learning of exceedingly long sequences while outperforming current online methods and approaching or outperforming offline methods on temporal classification tasks. The efficiency and robustness of FPTT enable us to directly train a deep and performant spiking neural network for joint object localization and recognition, demonstrating the ability to train large-scale dynamic and complex spiking neural network architectures. Memory efficient online training of recurrent spiking neural networks without compromising accuracy is an open challenge in neuromorphic computing. Yin and colleagues demonstrate that training a recurrent neural network consisting of so-called liquid time-constant spiking neurons using an algorithm called Forward-Propagation Through Time allows for online learning and state-of-the-art performance at a reduced computational cost compared with existing approaches.

Spiking Neural Networks (SNNs) offer a promising avenue for developing adaptive intelligence that can operate effectively, when subject to energy constraints. This is especially true for emerging gradient-based SNNs that are designed for continuous learning. However, hardware efficiency and complex SNN functionality are at odds with each other, leading to large design space, with many possible trade-offs. This paper discusses the co-optimization of SNNs and hardware architectures. We compare digital designs and emerging compute-in-memory architectures, in terms of operation. We discuss the effect of different layer-types on memory organization and outline how different memory organization schemes are impacted by the SNN layertype. Finally, we outline some open problems that must be solved to design the next-generation of intelligent hardware systems.

Neuromorphic computing has emerged as a highly promising paradigm for energy-efficient and real-time processing of event-driven workloads such as spiking neural networks (SNNs). These systems mimic the sparse and asynchronous communication behavior of the brain, and are particularly well-suited for edge AI, robotics, and low-power sensory processing. However, as neuromorphic processors scale to support larger and more complex SNNs, the communication infrastructure becomes a primary bottleneck. Conventional Network-on-Chip (NoC) architectures--while widely used in many-core systems--are ill-suited for neuromorphic workloads due to their reliance on area and energy intensive buffers, routing tables, and continuous link activity. Moreover, NoCs often fail to accommodate the bursty, multicast, and temporally sensitive nature of SNN traffic, leading to spike loss, latency variation, and unnecessary power dissipation. This dissertation introduces a comprehensive interconnect solution based on the segmented ladder bus, a lightweight and scalable bus architecture optimized for spiking communication. The first contribution is the design of ADIONA, a dynamic segmented ladder bus architecture that leverages bufferless switching and compile-time programmability to enable multiple concurrent paths with low energy and latency. ADIONA's segmented topology and runtime control provide flexibility while maintaining deterministic behavior and hardware simplicity. To support application-level deployment on ADIONA, the second major contribution is MASS--a mapping and scheduling framework for SNNs on segmented buses. MASS includes: (1) a heuristic-based cluster mapping strategy to minimize spike loss and communication energy, (2) a traffic scheduling algorithm to prevent path collisions through temporal grouping, and (3) a path routing method that minimizes path length and congestion. Experimental results show that MASS eliminates spike loss and reduces interconnect energy by up to 13.5% compared to randomized baselines, while supporting high-throughput traffic patterns. The final contribution is an efficient architecture proposal and a hardware realization of the control plane, via a scenario-aware controller implemented on FPGA. To manage control plane scaling complexity, we propose two algorithms--greedy grouping and maximal clique extraction--to compress switch control scenarios and minimize memory usage. Our FPGA results show that the control plane occupies less than 10% of the total area and scales sublinearly with the network size, validating the practicality of the approach. Together, these contributions form a complete and scalable communication framework for neuromorphic systems, spanning architectural design, algorithmic optimization, and hardware implementation. The segmented ladder bus offers a promising path toward future neuromorphic processors that demand low-power, low-latency, and scalable interconnects.

Ship voyage optimization for safe and energy-efficient navigation: A dynamic programming approach

Real-time target tracking is a usual task for humans despite the neural delays during the nervous system’s axonal transfer and neural processing. A plausible explanation is that the human brain employs predictive mechanisms to compensate for the delay. Inspired by the brain, this paper adopts a prediction network based on spiking neural networks (SNNs) to implement a real-time tracking task on a neuromorphic chip with low power consumption. The SNN-based prediction network outperforms the long short-term memory (LSTM) network on a small dataset and reduces 90% to 98% computations compared with LSTM. The quantized SNN-based network is deployed on a neuromorphic chip, and it takes 25ms and only 442 626nJ for a single prediction. The tracking performance of the system is also verified in real-life scenarios. Furthermore, the proposed real-time target tracking system can be easily ported to other neuromorphic platforms.