Equalized interconnects for on-chip networks: modeling and optimization framework

Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized—our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.

Design space exploration (DSE) is a common yet complex workflow in oilfield asset development. The "design" of an oilfield refers to a set of decisions about aspects ranging from well locations and number to facility sizing for optimum production. Evaluation of alternate designs – based extensively on reservoir simulations – corresponds to the evaluation of alternate development scenarios in face of uncertainty about subsurface structure and properties. The outputs of DSE influence many decisions in the development phase of an oilfield as well as operational decisions in a producing asset. In this work, we design and implement a generic framework to support DSE workflows in oilfield asset development. Our framework provides tools and services to allow rapid specification and evaluation of multiple design candidates using multiple realizations. The framework also supports hierarchical DSE workflows that allow users to first explore a large design space using proxy models and selectively refine the simulation quality of a smaller subset of designs via fine grained, detailed simulations. The usefulness of this framework is demonstrated through a case study that considers the design problem of selecting a drilling schedule for wells in an offshore oil and gas field.

This paper presents an FPGA emulation-based fast Network on Chip (NoC) prototyping framework, called Dynamic Reconfigurable NoC (DRNoC) Emulation Platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown

A regression-based design space exploration methodology is proposed that models the impacts of the memory hierarchy and the network-on-chip (NoC) on the overall chip multiprocessor (CMP) performance. Designers cannot explore all possible designs for a NoC without considering interactions with the rest of the uncore, in particular the cache configuration and memory hierarchy which determine the amount and pattern of the traffic on the NoC. The proposed regression model is able to capture the salient design points of the uncore for a comprehensive design space exploration by designing memory and NoC-specific regression models and leveraging recent advances in uncore simulation. To show the utility of our methodology, Uncore RPD, two case studies are presented: i) analyzing and refining regression models for an 8-core CMP and ii) performing a rapid design space exploration to find best performing designs of a NoC-based CMP given area-constraints for CMPs of up to 64 cores. Through these case studies, it is shown that i) simultaneous consideration of the memory and NoC parameters in the NoC design space exploration can refine uncore-based regression models, ii) sampling techniques must consider the dynamic design space of the uncore, and iii) overall, the proposed regression models reduce the amount of simulations required to characterize the NoC design space by up to four orders of magnitude.

In today’s computer architectures the design spaces are huge, thus making it very difficult to find optimal configurations. One way to cope with this problem is to use Automatic Design Space Exploration (ADSE) techniques. We developed the Framework for Automatic Design Space Exploration (FADSE) which is focused on microarchitectural optimizations. This framework includes several state-of-the art heuristic algorithms.In this paper we selected three of them, NSGA-II and SPEA2 as genetic algorithms as well as SMPSO as a particle swarm optimization, and compared their performance. As test case we optimize the parameters of the Grid ALU Processor (GAP) microarchitecture and then GAP together with the post-link code optimizer GAPtimize. An analysis of the simulation results shows a very good performance of all the three algorithms. SMPSO reveals the fastest convergence speed. A clear winner between NSGA-II and SPEA2 cannot be determined.

Computer architecture is transiting from the multicore era into the heterogeneous era in which heterogeneous architectures use on-chip networks to access shared resources and how a network is configured will likely have a significant impact on overall performance and power consumption. Recently, heterogeneous network on chip (NoC) has been proposed not only to achieve performance comparable to that of the NoCs with buffered routers but also to reduce buffer cost and energy consumption. However, heterogeneous NoC design for heterogeneous GPU-CPU architectures has not been studied in depth. This paper first evaluates the performance and power consumption of a variety of static hot-potato based heterogeneous NoCs with different buffered and bufferless router placements, which is helpful to explore the design space for heterogeneous GPU-CPU interconnection. Then it proposes Unidirectional Flow Control (UFC), a simple credit-based flow control mechanism for heterogeneous NoC in GPU-CPU architectures to control network congestion. UFC can guarantee that there are always unoccupied entries in buffered routers to receive flits coming from adjacent bufferless routers. Our evaluations show that when compared to hot-potato routing, UFC improves performance by an average of 14.1% with energy increased by an average of 5.3% only.

We present T&D-Bench, Teaching and Design Workbench, a framework for design space exploration of embedded processors. Design space exploration has become a fundamental phase of the SOC (System on a Chip) design process in industry and in research, and so it is important also in Computer Architecture education. T&D-Bench is an innovative framework to be employed in Computer Architecture education, providing the students a contact with a contemporary hardware design activity, and offering an easy and rapid design process, together with graphical user interface resources for tracking and steering the experiments with the processor models. T&D-Bench has been used at Universidade de Caxias do Sul since 2003 with positive results reported by the students, both beginners and seniors. T&D-Bench is available as an open source and platform-independent framework on the Internet.

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

To deal with large-scale problems that often occur in industry, the authors propose design space optimization with design space adjustment and refinement. In topology optimization, a design space is specified by the number of design variables, and their layout or configuration. The proposed procedure has two efficient algorithms for adjusting and refining design space. First, the design space can be adjusted in terms of design space expansion and reduction. This capability is evolutionary because the design domain expands or reduces wherever necessary. Second, the design space can be refined uniformly or selectively wherever and whenever necessary, ensuring a target resolution with fewer elements, especially for selective refinement. Accordingly, the proposed procedure can handle large-scale problems by solving a sequence of smaller problems. Two examples show the efficiency of the proposed approach.

Parametric modelling allows to relatively easily generate large sets of design variants (so called design space). Typically, a designer intuitively moves through this design space, resulting in one or several satisfying solutions. Due to the theoretically large number of variants that can be created with parametric models, obviously, there is a high probability that potentially good solutions could be missed, which is not at least because of human cognitive limitations. Consequently, it is necessary to develop a certain strategy to support designers in order to search for design solutions. Even though, various methods to systematically approach large data sets exist, the application of them in the design process is a special case, firstly, due to the existence of many non-specifiable and subjective dimensions (e.g. aesthetics) and secondly because of the multiple ways how designers actually search for solutions. This demands for a more flexible approach to design space exploration. This paper investigates how different methods can be combined to support the exploration of design spaces. Therefore, a conceptual framework with a modular architecture is proposed and its prototypical implementation is demonstrated.

Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers to explore the design space, verify functionality and estimate performance of designs. This paper presents a performance evaluation platform of NoC, which can measure and present performance of NoC designs at transaction-level, register-transfer-level and application-level of abstraction. Based on the hierarchical progressive abstraction approach, the platform has been built using SystemVerilog-based Transaction Level Modeling. This platform enables to generate various traffic patterns and support evaluation of multiple levels of service in NoC. Additionally, it is applicable to networks with arbitrary size, topology and multiple interface protocols. The effectiveness and correctness of this platform are verified by evaluating and analyzing specific NoC instances at the end of the paper.

Manufacturing is a promising technique for producing complex and custom-made parts with a high degree of precision. It can also provide us with desired materials and products with specified properties. To achieve that, it is crucial to find out the optimum point of process parameters that have a significant impact on the properties and quality of the final product. Unfortunately, optimizing these parameters can be challenging due to the complex and nonlinear nature of the underlying process, which becomes more complicated when there are conflicting objectives, sometimes with multiple goals. Furthermore, experiments are usually costly, time-consuming, and require expensive materials, man, and machine hours. So, each experiment is valuable and it's critical to determine the optimal experiment location to gain the most comprehensive understanding of the process. Sequential learning is a promising approach to actively learn from the ongoing experiments, iteratively update the underlying optimization routine, and adapt the data collection process on the go. This thesis presents a multi-objective Bayesian optimization framework to find out the optimum processing conditions for a manufacturing setup. It uses an acquisition function to collect data points sequentially and iteratively update its understanding of the underlying design space utilizing a Gaussian Process-based surrogate model. In manufacturing processes, the focus is often on obtaining a rough understanding of the design space using minimal experimentation, rather than finding the optimal parameters. This falls under the category of "approximating the underlying function" rather than design optimization. This approach can provide material scientists or manufacturing engineers with a comprehensive view of the entire design space, increasing the likelihood of making discoveries or making robust decisions. However, a precise and reliable prediction model is necessary for a good approximation. To meet this requirement, this thesis proposes an epsilon-greedy sequential prediction framework that is distinct from the optimization framework. The data acquisition strategy has been refined to balance exploration and exploitation, and a threshold has been established to determine when to switch between the two. The performance of this proposed optimization and prediction framework is evaluated using real-life datasets against the traditional design of experiments. The proposed frameworks have generated effective optimization and prediction results using fewer experiments.

Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. Research into the optimization of NoCs has shown that a reduction in the number of buffers in the NoC routers reduces the power and area overhead but degrades the network performance. In this paper, we propose iDEAL, a low-power area-efficient NoC architecture by reducing the number of buffers within the router. To overcome the performance degradation caused by the reduced buffer size, we propose to use adaptive dual-function links capable of data transmission as well as data storage when required. Simulation results for the proposed architecture show that reducing the router buffer size in half and using the adaptive dual-function links achieves nearly 40% savings in buffer power, 30% savings in overall network power and about 41% savings in the router area, with only a marginal 1-3% drop in performance. Moreover, the performance in iDEAL can be further improved by aggressive and speculative flow control techniques.

Network on Chips (NoC) have emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. The use of 3D IC technology in NoC promises to improve communication latency and power. Most of the 3D ICs use Through-silicon via (TSVs) as vertical interconnect. In this paper, we explore the design space of 2-layer 3D Butterfly Fat Tree (BFT) variants. Floorplan driven wire and TSV lengths are used to obtained power and performance optimal 3D NoC architectures. We analysed the performance of the output flow control using random and round robin output based deflection routing for 3D BFT variants. TSV based power and delay models were extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture. We propose a new OP3DBFT (Optimal Power and Performance 3DBFT) architecture with round-robin deflection routing (RROD) as power and performance optimal 2-layer 3D NoC architecture. OP3DBFT has symmetric link lengths and 75% of TSVs count reduced compared to the regular 2-layer 3D BFT topology. Results of our experiments show that the performance improved up to 1.39\(\times \) and 1.3\(\times \) in OP3DBFT with fewer TSV counts compared to the regular 2-layer 3D BFT for uniform and transpose traffic respectively. The OP3DBFT NoC architecture EDP (Energy delay product) was lower by 40% for uniform traffic and 48% for transpose traffic.

A framework for the design, modeling and optimization of biomedical systems