Design Space Exploration of Embedded Processors in Computer Architecture Education using T&D-Bench

With the improvement of integration degree, more and more systems that originally implemented on PCB board are integrated into one chip, becoming a SOC (system on a chip). Also with the increasing demand for programmable performance, the use of multi microprocessors structure in SOC designs is becoming much more popular. For the complex real-time systems such as HDTV decoder, it is generally easier with multiple CPUs to provide instant response time and meet the demand of real-time and function complexity. In this paper, based on introduction of the HDTV SOC architecture we designed, a communication and control scheme between master-slave mode dual-processors in the SOC is proposed, as well as a shared memory control method among multi IP function modules in the SOC.

With the emergence of approximate computing as a design paradigm, many approximate functional units have been proposed, particularly approximate adders and multipliers. These circuits compromise the accuracy of their results within a tolerable limit to reduce the required computational effort and energy requirements. However, for an ongoing number of such approximate circuits reported in the literature, selecting those that minimize the required resources for designing and generating an approximate accelerator from a high-level specification, while satisfying a defined accuracy constraint, is a joint high-level synthesis (HLS) and design space exploration (DSE) challenge. In this paper, we propose a novel automated framework for HLS of approximate accelerators using a given library of approximate functional units. Since repetitive circuit synthesis and gate-level simulations require a significant amount of time, to enable our framework, we present AxME, a set of analytical models for estimating the required computational resources when using approximate adders and multipliers in approximate designs. We propose DSEwam, a DSE methodology for error-tolerant applications, in which analytical models, such as AxME, are used to estimate resources needed and the accuracy of approximate designs. Furthermore, we integrate DSEwam into an HLS tool to automatically generate Pareto-optimal, or near Pareto-optimal, approximate accelerators from C language descriptions, for a given error threshold and minimization goal. We release our DSE framework as an open-source contribution, which will significantly boost the research and development in the field of automatic generation of approximate accelerators.

Manufacturing process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90nm CMOS technologies. Process variability impacts the optimization of the target system metrics, that is, performance and energy consumption by introducing fluctuations and unpredictability. Besides, it impacts the parametric yield of the chip with respect to application level constraints by reducing the number of devices working within normal operating conditions. The impact of variability on systems with stringent application-specific requirements (such as portable multimedia and critical embedded systems) is much greater than on general-purpose systems given the emphasis on predictability and reduced operating margins. In this market segment, failing to address such a problem within the early design stages of the chip may lead to missing market deadlines and suffering greater economic losses. In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we apply Response Surface Modeling (RSM) techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. Then, we apply a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches on two different case studies.

The need to efficiently execute different Deep Neural Networks (DNNs) on the same computing platform, coupled with the requirement for easy scalability, makes Multi-Chip Module (MCM)-based accelerators a preferred design choice. Such an accelerator brings together heterogeneous sub-accelerators in the form of chiplets, interconnected by a Network-on-Package (NoP). This paper addresses the challenge of selecting the most suitable sub-accelerators, configuring them, determining their optimal placement in the NoP, and mapping the layers of a predetermined set of DNNs spatially and temporally. The objective is to minimise execution time and energy consumption during parallel execution while also minimising the overall cost, specifically the silicon area, of the accelerator. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">This paper presents MOHaM, a framework for multi-objective hardware-mapping co-optimisation for multi-DNN workloads on chiplet-based accelerators. MOHaM exploits a multi-objective evolutionary algorithm that has been specialised for the given problem by incorporating several customised genetic operators. MOHaM is evaluated against state-of-the-art Design Space Exploration (DSE) frameworks on different multi-DNN workload scenarios. The solutions discovered by MOHaM are Pareto optimal compared to those by the state-of-the-art. Specifically, MOHaM-generated accelerator designs can reduce latency by up to 96% and energy by up to 96.12%.

Building performance simulations (BPS) are essential for managing rising energy demands but are computationally intensive, limiting their use in early-stage design. Surrogate models (SMs) offer fast approximations using machine learning but lack generalizability for changing building morphologies. This study introduces three morphology-based feature extraction methods – Zernike image moments, polar raycasting, and principal component analysis – to train a generalizable SM for predicting annual energy use intensity (EUI) of 2.5D residential buildings in Singapore. The best SM achieved a 9.2% RMSPE, with features yielding low error and avoiding overfitting. This framework enables efficient design space exploration, aiding architects and urban designers in optimizing masterplans for energy efficiency. In the final section, we demonstrate a design space exploration (DSE) framework with our generalizable SM using a novel parametric model, showcasing its speed, adaptability and convenience over conventional optimization workflows. Highlights Novel approach explores building morphology's impact to annual EUI . Using Zernike moments, ray casting and PCA to extract features from any 2.5D buildings. 4000 tuned SMs trained from hyperparameter optimisation. Most robust SM achieved 9.2% RMSPE when tested with 800 samples. SM's generalizability is proven by applying it to a design model with previously unseen parameters.

As modern FPGAs continue to scale, the routing architecture increasingly dominates both area and delay. However, traditional homogeneous routing architectures struggle to efficiently accommodate spatially varying routing demands, often resulting in imbalanced routing resource utilization across different regions. This inefficiency contributes to increased routing area and critical path delay (CPD). To address this limitation, this paper proposes a hybrid FPGA routing architecture that introduces spatial heterogeneity into interconnect block configurations. The proposed architecture is fully parameterized, allowing different regions of the FPGA fabric to adopt distinct routing topologies tailored to local connectivity requirements. To support this architecture within the Verilog-to-Routing (VTR) toolchain, we extend the architecture description file format and enhance the routing resource graph (RRG) generator to support region-specific interconnect features. Furthermore, to efficiently search the vast parameter space, we employ a parallel Bayesian optimization (BO)-based design space exploration (DSE) framework for automated identification of optimal architecture configurations. Experimental results on the VTR benchmark suite demonstrate that the proposed hybrid routing architecture achieves up to 7.9% reduction in routing area, 2.5% improvement in CPD, and 10.1 % improvement in area-delay product (ADP) compared to the state-of-the-art VIB architecture. Additional analysis also shows a 38.09 % reduction in routing detour, confirming the effectiveness of the hybrid architecture in improving routing compactness and reducing wire overhead.

Real-time multimedia applications are increasingly being mapped onto MPSoC (multiprocessor system-on-chip) platforms containing hardware--software IPs (intellectual property), along with a library of common scheduling policies such as EDF, RM. The choice of a scheduling policy for each IP is a key decision that greatly affects the design's ability to meet real-time constraints, and also directly affects the energy consumed by the design. We present a cosynthesis framework for design space exploration that considers heterogeneous scheduling while mapping multimedia applications onto such MPSoCs. In our approach, we select a suitable scheduling policy for each IP such that system energy is minimized—our framework also includes energy-reduction techniques utilizing dynamic power management. Experimental results on a realistic multimode multimedia terminal application demonstrate that our approach enables us to select design points with up to 60.5% reduced energy for a given area constraint, while meeting all real-time requirements. More importantly, our approach generates a tradeoff space between energy and cost allowing designers to comparatively evaluate multiple system level mappings.

Design space exploration (DSE) is a common yet complex workflow in oilfield asset development. The "design" of an oilfield refers to a set of decisions about aspects ranging from well locations and number to facility sizing for optimum production. Evaluation of alternate designs – based extensively on reservoir simulations – corresponds to the evaluation of alternate development scenarios in face of uncertainty about subsurface structure and properties. The outputs of DSE influence many decisions in the development phase of an oilfield as well as operational decisions in a producing asset. In this work, we design and implement a generic framework to support DSE workflows in oilfield asset development. Our framework provides tools and services to allow rapid specification and evaluation of multiple design candidates using multiple realizations. The framework also supports hierarchical DSE workflows that allow users to first explore a large design space using proxy models and selectively refine the simulation quality of a smaller subset of designs via fine grained, detailed simulations. The usefulness of this framework is demonstrated through a case study that considers the design problem of selecting a drilling schedule for wells in an offshore oil and gas field.

Parametric modelling allows to relatively easily generate large sets of design variants (so called design space). Typically, a designer intuitively moves through this design space, resulting in one or several satisfying solutions. Due to the theoretically large number of variants that can be created with parametric models, obviously, there is a high probability that potentially good solutions could be missed, which is not at least because of human cognitive limitations. Consequently, it is necessary to develop a certain strategy to support designers in order to search for design solutions. Even though, various methods to systematically approach large data sets exist, the application of them in the design process is a special case, firstly, due to the existence of many non-specifiable and subjective dimensions (e.g. aesthetics) and secondly because of the multiple ways how designers actually search for solutions. This demands for a more flexible approach to design space exploration. This paper investigates how different methods can be combined to support the exploration of design spaces. Therefore, a conceptual framework with a modular architecture is proposed and its prototypical implementation is demonstrated.

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modelling at a higher level of design abstraction, that is, the electronic system level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modelling of the hardware and the software parts of the system, and the interprocess communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also be carried out with a high simulation speed. A case study of a SoC implementing elliptic curve cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality verification and design space exploration.

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

In recent years the Run-Time-Reconfigurable (RTR) computing systems have become the core of next generation of adaptive embedded systems. One of the major problems in this class of systems is run-time adaptation of their architecture to the dynamic workload and environmental conditions. In most cases this adaptation is considered as multi-objective optimization process which should be conducted in run-time. Therefore, the goal of this research work was to explore the existing methods of doing multi-objective optimization and analyze their applicability for a system with potential of reconfiguration (i.e. a situation when constrains of the system can change during the course of operation). Then the development of generic framework of this optimization mechanism has to be done. This required analysis and selection of proper approach for multi-objective space exploration. The methodology based on Architecture Configuration Graph was chosen and its searching technique improved to allow faster convergence to a solution that satisfies objective constraints while optimizing specified objective. The run-time complexity analysis was done for modified methodology as well as the testing of the implemented framework to demonstrate its faster performance. The experimental results have shown the ability for run-time architecture adaptation and further utilization of the proposed framework as a core of real-time operating systems (RTOS) for dynamically reconfigurable computers.