Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

Scalability tests are a common method to verify the adaptability of software components. When developing embedded systems, these tests could be put into practice by increasing the number of computing cores, as well as by changing the underlying processor architecture, for example. Therefore, it is common practice to utilize reconfigurable virtual platforms for embedded software scalability tests and design space exploration. Nevertheless, setting up proper test cases, consisting of distinct virtual platform configurations, toolchains, linker scripts and startup codes requires in-depth knowledge in hardware development. Therefore, in order to offer software engineers the possibility to create and operate a variety of possible virtual heterogeneous embedded multi core platforms for testing purposes on their own, this paper introduces a tool set for creating virtual platforms including appropriate toolchains and build environments from a software engineer’s point of view. The feasibility of our tool set was evaluated in a user-centered case study. Hence, a group of software engineers are asked to perform certain tasks in the field of embedded multi core programming.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing sys-tem design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, software development and performance evaluation of these massively parallel architectures. However, architectural simulation performance is a serious concern, as virtual platforms and simulation technology are not able to tackle the complexity of thousands of core future scenarios. The main contribution of this paper is the development of a new simulation approach and technology for many core processors which exploit the enormous parallel processing capability of low-cost and widely available General Purpose Graphic Processing Units (GPGPU). The simulation of many-core architectures exhibits indeed a high level of parallelism and is inherently parallelizable, but GPGPU acceleration of architectural simulation requires an in-depth revision of the data structures and functional partitioning traditionally used in parallel simulation. We demonstrate our GPGPU simulator on a target architecture composed by several cores (i.e. ARM ISA based), with instruction and data caches, connected through a Network-on-Chip (NoC). Our experiments confirm the feasibility of our approach.

Many demanding streaming applications share functional and structural similarities with other applications in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization to achieve the needed efficiency and/or performance.Platforms integrating many accelerators (ACCs) are a primary approach for efficient, high-performance stream computing. However, designing one platform for each application is not economical due to the high costs of nonrecurring engineering (NRE) and time-to-market (TTM). To this end, the concept of domain platforms is proposed, which takes advantage of similarities across applications and designs one unified platform to accelerate a domain of applications instead of focusing on a single reference application. This dissertation approaches designing domain platforms from a function-level (kernel-level) acceleration through a heterogeneous ACC-rich platform, where each ACC is specialized to accelerate a particular function. There is a great challenge to select ACCs allocated in the domain platform, considering the large design space and performance balance across many applications. However, current Design Space Exploration (DSE) tools only focus on an individual application in isolation (e.g., one particular vision flow) for allocating a platform, but not a set of similar applications. Multiple applications are only considered in the application bindings to an existing platform. Hence, optimizations that occur due to considering multiple applications simultaneously are missed in platform design. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This dissertation introduces a novel Domain Design Space Exploration (DmDSE) methodology that broadens the DSE scope from an individual application to allocating a new heterogeneous ACC-rich platform for many applications.This dissertation defines domain characteristics to express the inherent structural and functional similarities across applications and metrics to quantitatively assess domain platforms with a balanced focus across various applications. Two novel algorithms, Dynamic Score Selection (DSS) and GenetIc Domain Exploration (GIDE), are introduced to do DmDSE and allocate domain platforms, which improve performance over application-specific platforms by 58% and 75% when only considering monolithic (single function) ACCs. A finer granularity of ACCs is beneficial for generality and performance under an area constraint. Considering multi-granularity similarities across functions, Multi-Granularity DmDSE (MG-DmDSE) extends DSE through allocating finer granular and configurable ACCs and decomposing functions in the binding. MG-DmDSE produces a more general platform that benefited 87.5% of applications, while only 50% from GIDE. With a huge design space, DmDSE suffers from a long exploration time due to a large number of complex platform evaluations. Heuristics and machine learning methods are proposed to speed up DmDSE.This dissertation introduces Greedy Guided Mutation (GGM) to speed up the mutation in the GIDE algorithm, which calculates an ACC score according to current allocation to guide mutation. Alternatively, Rapid Domain Platform Performance Prediction (RDP^3) methods are introduced to replace a large number of the slow platform assessment in domain DSE, which avoids the complex application binding exploration. In the experiments, GGM reduces 84.8% of exploration time with a 0.23% loss of the final OpenVX domain platform's performance. RDP^3, using a machine learning method, yields an even more significant speedup, saving 90.8% of exploration time with only 0.0003% performance loss. DmDSE is a milestone to broaden DSE scope from individual applications to the domain level. It tremendously pushes the domain platform design from an experience-guided, manual effort into an automated process.--Author's abstract

The steady increase in complexity of high-end embedded systems goes along with an increasingly complex design process. We are currently still in a transition phase from Hardware-Description Language (HDL) based design towards virtual-platform-based design of embedded systems. As design complexity rises faster than developer productivity a gap forms. Restoring productivity while at the same time managing increased design complexity can also be achieved through focussing on the development of new tools and design methodologies. In most application areas, high-level modelling languages such as SystemC are used in early design phases. In modern software development Continuous Integration (CI) is used to automatically test if a submitted piece of code breaks functionality. Application of the CI concept to embedded system design and testing requires fast build and test execution times from the virtual platform framework. For this use case the ability to save a specific state of a virtual platform becomes necessary. The saving and restoring of specific states of a simulation requires the ability to serialize all data structures within the simulation models. Improving the frameworks and establishing better methods will only help to narrow the design gap, if these changes are introduced with the needs of the engineers and developers in mind. Ultimately, it is their productivity that shall be improved. The ability to save the state of a virtual platform enables developers to run longer test campaigns that can even contain randomized test stimuli. If the saved states are modifiable the developers can inject faulty states into the simulation models. This work contributes an extension to the SoCRocket virtual platform framework to enable snapshotting. The snapshotting extension can be considered a reference implementation as the utilization of current SystemC/TLM standards makes it compatible to other frameworkds. Furthermore, integrating the UVM SystemC library into the framework enables test driven development and fast validation of SystemC/TLM models using snapshots. These extensions narrow the design gap by supporting designers, testers and developers to work more efficiently.

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

The main objective of paper is to design and implement a high speed processing system with high throughput and low complexity. We are using system on chip using AMBA bus. This high speed processing system is application specific. This system will be used for landmine detection during wars as high speed processing is need of application. Firstly input processor will be designed as per the application. Then the concurrent processor will be designed. VHDL coding of the entire system on chip will be done. The simulation will be performed using Xilinx and FPGA. After the processing system is designed it will be compared to the conventional controller system. Thus proving that the system on chip is efficient and fast processing than the controller system.

This paper presents our new developed FOCAP tool (Framework for optimizing the Computer Architecture Performance) in order to gain a better understanding and familiarity of the students with new advanced learning methods and tools in the Microarchitecture Simulation and Optimization. At this stage, FOCAP allows a mono-objective automatic design space exploration (DSE) of a superscalar processor by varying several architectural parameters. Such DSE tools are very useful, since it is impossible to simulate all the configurations of a highly parameterized microarchitecture. Therefore, heuristic methods, local search algorithms and advanced machine learning methods are good candidates to find near-optimal configurations by evaluating a reduced number of configurations from the huge design space. Our application falls in the European trend of Framework projects that aim expanding research towards the advanced education field using modern learning technologies. The FOCAP tool facilitates the comprehending of theoretical questions, thus allowing students to feel more confident when studying microarchitecture optimization and DSE-related issues.

The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design methods, can result in extremely long simulation time compounded with time-consuming verification process. Hence, today digital system design begins with modelling at a higher level of design abstraction, that is, the electronic system level (ESL). This paper presents a hardware-software (HW/SW) co-simulation environment based on SystemC for application in the design of system-on-chip (SoC). We discuss the SystemC modelling of the hardware and the software parts of the system, and the interprocess communication module of the co-simulation platform. Its objective is to help designers obtain an appropriate HW/SW partitioning that satisfy specified area-speed design tradeoffs. Besides, an early system verification can also be carried out with a high simulation speed. A case study of a SoC implementing elliptic curve cryptography (ECC) is presented to validate the co-simulation platform in terms of system functionality verification and design space exploration.

Advances in semiconductor manufacturing still lead to ever decreasing feature sizes and constantly allow higher degrees of integration in application specific integrated circuits (ASICs). Therefore the bandwidth requirements on the external interfaces of such systems on chips (SoC) are steadily growing. Yet, as the number of pins on these ASICs is not increasing in the same pace - known as pin limitation - the bandwidth per pin has to be increased. SerDes (Serializer/Deserializer) technology, which allows to transfer data serially at very high data rates of 25Gbps and more is a key technology to overcome pin limitation and exploit the computing power that can be achieved in todays SoCs. As such SerDes blocks together with the digital logic interfacing them form complex mixed signal systems, verification of performance and functional correctness is very challenging. In this thesis a novel mixed-signal design methodology is proposed, which tightly couples model and implementation in order to ensure consistency throughout the design cycles and hereby accelerate the overall implementation flow. A tool flow that has been developed is presented, which integrates well into state of the art electronic design automation (EDA) environments and enables the usage of this methodology in practice. Further, the design space of todays high-speed serial links is analyzed and an architecture is proposed, which pushes complexity into the digital domain in order to achieve robustness, portability between manufacturing processes and scaling with advanced node technologies. The all digital phase locked loop (PLL) and clock data recovery (CDR), which have been developed are described in detail. The developed design flow was used for the implementation of the SerDes architecture in a 28nm silicon process and proved to be indispensable for future projects.

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP).Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 μm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to market, thus how to verify IP functionality on bus protocol is challenge. Traditional simulation-based bus protocol monitor scan check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule based bus protocol checker, it contain ns 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently Keywords: Arbiter, Reconfigurable, System-on-chip, Arbitration Algorithm, FPGA, AMBA

As the communication sub-system that connecting various on-chip components, Network-on-Chip (NoC) has a great influence on the performance of multi-/many-core processors. Because of NoC model contains a large number of parameters, the design space exploration (DSE) for NoC is a critical problem for the architects. Similar to the core design, existing DSE process mainly depends on iteratively time-consuming simulations. To lower the time budget, many previous studies focus on reducing the simulations. However, most of the proposed works based on regression or machine learning techniques, whose accuracy will be significantly affected by the scale of training set. It still needs a lot of simulations to build the training set.

Solid State Drives (SSDs) are gaining particular momentum in various frameworks such as multimedia, large data centers and cloud environments. Unfortunately, efficient CAD tools for SSD design space exploration able to assess the optimization of the device microarchitecture w.r.t. the target performance are still missing. This paper tries to close this gap by proposing SSDExplorer, a tool for fine-grained and fast design space exploration of SSD devices. SSDExplorer provides unprecedented insights into the architecture behavior and subcomponent interaction efficiency, while avoiding the need for the actual implementation of an FTL or of key hardware components. This is achieved by the introduction of suitable abstractions of the different components. This is confirmed by the thorough validation of SSDExplorer against a commercial SSD device.

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