SOC for detecting landmines

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

A system on a chip (SoC) for a motion controller using a field-programmable gate array (FPGA) and ARM processors is developed, and a task-partitioning technique is presented. Motion control requires fast and real-time input and output and the FPGA is a good tool to manage them. However, flexible and complex command generations are difficult to implement. Here, the SoC FPGA is a good solution because it has processors beside the FPGA. In designing on this platform, a feedback controller achieving high robustness is on the FPGA, and a feedforward controller determining a motion is on the processor. Then, a disturbance observer (DOB), one of the 2-degree-of-freedom (DOF) controllers, and an acceleration controller are introduced to decouple these designs. The DOB is simple to design with a few parameters and then provides a general framework for motion control. Introduction of the SoC FPGA enables to attain both the high robustness and the flexible command generation.

This paper presents a System on a Chip (SoC) Field-Programmable Gate Array (FPGA) implementation for Media Access Control (MAC) layer of a fast industrial Wireless Local Area Network (iWLAN) protocol, which is used to control industrial robots in factory automation environments. This protocol is a potential technique for industrial wireless communication system by using the Low overhead Packet Division Multiple Access (PDMA) scheme controlled by MAC layer. In our previous research, the MAC layer hardware was implemented and tested on simulation software, but the SoC design for the MAC layer has not been implemented and real tested on the FPGA. In this paper, we have successfully implemented the SoC system for MAC layer of this high-speed wireless communication protocol on the FPGA.

The future of the autonomous cart follower system will be equipped with lots of sensory data, due to the ever lower cost of sensory devices. This provides design challenge on handling large data and firmware complexity. This paper investigates an alternative approach of running the autonomous cart follower system on neural network model using Field Programmable Gates Array (FPGA). A microcontroller based autonomous cart follower system is modified to use the FPGA board and implemented via the System on Chip (SOC) approach. The neural network model is trained off line then implemented as software code in the SOC. By observation the firmware footprint of the neural network model remains small size regardless of the neural network size. The result shows that with 40 % more additional resource utilization, the overall system improvement of 27 times is achieved with the usage of hardware acceleration block in SOC compared to SOC without hardware acceleration.

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP).Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 μm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to market, thus how to verify IP functionality on bus protocol is challenge. Traditional simulation-based bus protocol monitor scan check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule based bus protocol checker, it contain ns 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently Keywords: Arbiter, Reconfigurable, System-on-chip, Arbitration Algorithm, FPGA, AMBA

In this paper we explain how the POEtic chip can be used for rapid prototyping. The POEtic chip, currently in the test phase, is a system-on-chip (SoC) containing a microprocessor and a reconfigurable array. Special features allow the dynamic creation of data paths in the reconfigurable array at runtime. It has been specially designed to ease the development of bio-inspired systems such as neural networks, but can serve as a general purpose platform, or as a prototype for hardware/software codesign. An AMBA bus allows POEtic chips to be connected to each other, or to external devices. After describing the hardware SoC, we discuss the software tools that have been created to design and test different applications. Three of these applications are described in order to demonstrate the utility of the POEtic chip's special features.

Field-Programmable Gate Arrays (FPGAs) have become a mainstay in the digital electronics world both for the ease of implementation as well as their inherent usefulness in incrementally refining hardware designs. When moving to an Application Specific Integrated Circuit (ASIC) or System on a Chip (SoC), verification becomes a very time consuming process, with virtually no room for error. As a result, a variety of methods have been devised to decrease the risk when creating an ASIC or SoC. We describe a hardware and software framework for testing real-time vision algorithms for lowering the uncertainty in FPGA and SoC development, while reducing the SoC verification time. The framework benefits from hardware and software verification, ease of reconfiguration for testing multiple vision algorithms, and an iterative hardware/ software co-design.

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

Due to technology progress, one full system, for example: a computer or a DVD player can be made as a single IC chip. This type of IC chip is called System on Chip (SOC) IC. SOC IC is important for the future of IC industry. A company, no matter of an IC design company, an IC test company or an IC test equipment supplier, all of them need to develop new business strategies in order to win the emergent SOC IC market. The case study focuses on the analysis of IC test and IC test equipment supplier-the “A” company, for its future developments and business strategies of SOC IC test market. We use R.K. Yin ”Case Study Research: Design and Methods (2003) to build up the case research process. This study concludes that “technology” is the key success factor of IC test equipment industry, and it is also A company’s competitive advantage. The IC test equipment supplier should use diversification and differentiation business strategies to win the SOC IC test equipment market. Results also show that A company’s strategies for SOC IC test equipment market come along with theoretic strategies such as the differentiation strategy of Michael E. Porter (1980) and the diversification strategy of Ansoff (1975).

With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.

Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

The field of Internet of Things (IoT) and smart sensors has expanded rapidly in various fields of research and industrial applications. The area of IoT robotics has become a critical component in the evolution of Industry 4.0 standard. In this paper, we developed an IoT based reconfigurable System on Chip (SoC) robot that is fast and efficient for computer vision applications. It can be deployed in other IoT robotics applications and achieve its intended function. A Terasic Hexapod Spider Robot (TSR) was used with its DE0-Nano SoC board to implement our IoT robotics system. The TSR was designed to provide a competent computer vision application to recognize different shapes using a machine learning classifier. The data processing for image detection was divided into two parts, the first part involves hardware implementation on the SoC board and to provide real-time interaction of the robot with the surrounding environment. The second part of implementation is based on the cloud processing technique, where further data analysis was performed. The image detection algorithm for the computer vision component was tested and successfully implemented to recognize shapes. The TSR moves or reacts based on the detected image. The Field Programmable Gate Array (FPGA) part is programmed to handle the movement of the robot and the Hard Processor System (HPS) handles the shape recognition, Wi-Fi connectivity, and Bluetooth communication. This design is implemented, tested and can be used in real-time applications in harsh environments where movements of other robots are restricted.

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

To heighten the biometrics security level, the biometrics feature extraction and verification need to be performed within smart cards, not in external card readers. However, the smart card chip has very limited processing capability, and typical fingerprint feature extraction and verification algorithms may not be executed on a state-of-the-art smart card. Therefore, this paper presents a system-on-chip (SoC) implementation of the fingerprint feature extraction algorithm which can be integrated into smart cards. To implement the ridge-following algorithm onto the resource-constrained SoCs, the algorithm has been modified to increase the efficiency of the hardware. Each functional block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The proposed system operated in 50MHz, and 20~50 minutiae could be extracted from typical 248timestimes292 fingerprint images in real time with our small area implementation (97K gates). Our current implementation developed as an IP for SoCs targeted for ARM CPU and AMBA bus can also be extended for many other smart card configurations