System-on-a-Chip Including Generic Framework of Motion Controller Using Disturbance Observer Based Acceleration Controller

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

This paper presents a System on a Chip (SoC) Field-Programmable Gate Array (FPGA) implementation for Media Access Control (MAC) layer of a fast industrial Wireless Local Area Network (iWLAN) protocol, which is used to control industrial robots in factory automation environments. This protocol is a potential technique for industrial wireless communication system by using the Low overhead Packet Division Multiple Access (PDMA) scheme controlled by MAC layer. In our previous research, the MAC layer hardware was implemented and tested on simulation software, but the SoC design for the MAC layer has not been implemented and real tested on the FPGA. In this paper, we have successfully implemented the SoC system for MAC layer of this high-speed wireless communication protocol on the FPGA.

The future of the autonomous cart follower system will be equipped with lots of sensory data, due to the ever lower cost of sensory devices. This provides design challenge on handling large data and firmware complexity. This paper investigates an alternative approach of running the autonomous cart follower system on neural network model using Field Programmable Gates Array (FPGA). A microcontroller based autonomous cart follower system is modified to use the FPGA board and implemented via the System on Chip (SOC) approach. The neural network model is trained off line then implemented as software code in the SOC. By observation the firmware footprint of the neural network model remains small size regardless of the neural network size. The result shows that with 40 % more additional resource utilization, the overall system improvement of 27 times is achieved with the usage of hardware acceleration block in SOC compared to SOC without hardware acceleration.

This paper presents a Field Programmable Gate Array (FPGA) -based platform for integrated multi-axis motion control and motor drive. As the development of FPGA, the integrated high-performance ARM processor on the FPGA has become the direction of FPGA development. This paper chooses the Xilinx Zynq-7020 programmable system-on-chip(SoC) which integrated dual-core ARM CPU and FPGA as a High-performance hardware platform. This platform is suits for the requirements of integrated multi-axis motion control and motor drive well, one ARM CUP completes the multi-axis position loop algorithm, speed loop algorithm and multi-axis trajectory generation, the other completes the human-computer interaction function. 4-axis current loop pipeline control and double sampling double updating current loop algorithm are accomplished by FPGA which can expand the current loop bandwidth and save FPGA logic resources. This platform’s architecture will improve the overall bandwidth of the system, achieve multi-axis synchronization accuracy at nanosecond level which makes position trajectory more accurate.

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

Field-Programmable Gate Arrays (FPGAs) have become a mainstay in the digital electronics world both for the ease of implementation as well as their inherent usefulness in incrementally refining hardware designs. When moving to an Application Specific Integrated Circuit (ASIC) or System on a Chip (SoC), verification becomes a very time consuming process, with virtually no room for error. As a result, a variety of methods have been devised to decrease the risk when creating an ASIC or SoC. We describe a hardware and software framework for testing real-time vision algorithms for lowering the uncertainty in FPGA and SoC development, while reducing the SoC verification time. The framework benefits from hardware and software verification, ease of reconfiguration for testing multiple vision algorithms, and an iterative hardware/ software co-design.

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.KeywordsHigh-level synthesis (HLS)Neural networks (NNs)Register transfer level (RTL)Field-programmable gate arrays (FPGAs)Systems on chip (SOC)Artificial intelligence (AI)Graphic processing units (GPUs)Generalized NNs (GNN)Recurrent neural network (RNN)Feed-forward neural networks (FFNNs)

The performances of System on Chip (SoC) and the Field Programmable Gate Array (FPGA) particularly, are increasing continually. Due to the growing complexity of modern embedded control systems, the need of more performance digital devices is evident. Recent FPGA technology makes it possible to include processor cores into the FPGA chip, which ensures more flexibility for digital controllers. Indeed, greater functionality of hardware and system software, Real-Time (RT) platforms and distributed subsystems are demanded. In this chapter, a design concept of FPGA based controller with Hardware/Software (Hw/Sw) codesign is proposed. It is applied for electrical machine drives. There are discussed different MultiProcessor SoC (MPSoC) architectures with Hw peripherals for the implementation on FPGA-based embedded processor cores. Hw accelerators are considered in the design to enhance the controller speed performance and reduce power consumption. Test and validation of this control system are performed on a RT motor emulator implemented on the same FPGA. Experimental results, carried on a real prototyping platform, are given in order to analyze the performance and efficiency of discussed architecture designs helping to support hard RT constraints.Request access from your librarian to read this chapter's full text.

Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.

Field Programmable Gate Arrays (FPGAs) have gained popularity because their reconfigurability can speed up development and verification with relatively low cost. However the deep level of understanding required on hardware logic programming has discouraged many software engineers. An interface between host devices and FPGAs to enable designing and programming FPGAs using a software programming standard and encapsulating hardware details is much desired. In this paper we evaluate leveraging Open Computing Language (OpenCL) to rapidly design FPGAs, considering both hardware logic utilization efficiency and computing performance. On a heterogeneous computer system consisting of ARM processors and Altera FPGA, we execute an OpenCL host program on the ARM processors and an OpenCL kernel on the FPGA, to compute a parametrizable two-dimensional Mandelbrot fractal. We explore three design aspects of adjusting OpenCL work-group size, coalescing memory access, and replicating compute units to improve the FPGA computation performance. After optimizing the core algorithm, we efficiently reduced the logic utilization and Digital Signal Processing (DSP) blocks required for a single compute unit, and successfully increased the number of replicated compute units from four to six, thus delivering a 1.5X increase of parallel computation capacity of the FPGA, and improving the computing speed by 1.5X and memory bandwidth by 1.7X.