Inter multi processor communication scheme and shared memory control in the HDTV decoder SOC design

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

Embedded systems are increasingly synthesized today as systems-on-a-chip (SOCs), wherein existing functional blocks (also called cores) are used to implement different functions in the system specification. Emphasis during system synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a postprocessing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, performing test modifications after the SOC design has been optimized for target design constraints does not preserve the optimality of the solution obtained. In this paper, the authors present the first system-level synthesis for testability framework that integrates testability considerations into the synthesis process. Their work incorporates finite-state automata (FSA)-based symbolic testability analysis within the framework of an existing multiobjective optimization-based system synthesis tool to provide a viable solution. The experimental results show that the use of FSA-based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. System synthesis through the integrated framework for a number of examples indicates that efficient SOC architectures, which tradeoff different architectural features such as integrated circuit price, power consumption, and area under real-time constraints, can now be easily generated with low testability costs.

Motion estimation algorithm plays a crucial role in video coding/processing and accounts for almost one quarter of the gate count or area in many digital video system-on-a-chip (SoC) due to its computational intensive nature. In this paper, we present a complexity-reduced three dimensional (3D) motion estimator (ME) which reduces the number of search candidates and hence gate count significantly. Moreover, by virtue of its recursive architecture, hardware estimated sum of absolute differences (SAD) and motion vectors (MV) can be passed backed to the embedded DSP processor for image segmentation, resulting in efficient software/hardware partition in SoC designs. In addition, the calculated SAD's can also be further analyzed by the embedded CPU for rate control in video coding. Alleviating traditional ME artifacts such as illumination, this motion estimator with segmentation capabilities is readily applicable to video object planes (VOP) processing in levels higher than the advance simple profile in MPEG4, H.264 and motion compensated format converters such as deinterlacers and scan-rate converters.

This paper presents a System on a Chip (SoC) Field-Programmable Gate Array (FPGA) implementation for Media Access Control (MAC) layer of a fast industrial Wireless Local Area Network (iWLAN) protocol, which is used to control industrial robots in factory automation environments. This protocol is a potential technique for industrial wireless communication system by using the Low overhead Packet Division Multiple Access (PDMA) scheme controlled by MAC layer. In our previous research, the MAC layer hardware was implemented and tested on simulation software, but the SoC design for the MAC layer has not been implemented and real tested on the FPGA. In this paper, we have successfully implemented the SoC system for MAC layer of this high-speed wireless communication protocol on the FPGA.

The higher integration of the system‐on‐a‐chip (SoC) has intensified the need for a system‐on‐a‐chip design platform with a built‐in microcomputer. An important element in SoC design with a built‐in microcomputer is the debugging function. Here, we developed an SoC design platform equipped with a debugging interface shared by the microcomputer. By adopting the design methodology using this platform, we can shorten the SoC design period because we can concentrate on the new design or customization of the important hardware and software of the system and can nearly simultaneously start software and hardware development. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(5): 13–23, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10192

We present T&D-Bench, Teaching and Design Workbench, a framework for design space exploration of embedded processors. Design space exploration has become a fundamental phase of the SOC (System on a Chip) design process in industry and in research, and so it is important also in Computer Architecture education. T&D-Bench is an innovative framework to be employed in Computer Architecture education, providing the students a contact with a contemporary hardware design activity, and offering an easy and rapid design process, together with graphical user interface resources for tracking and steering the experiments with the processor models. T&D-Bench has been used at Universidade de Caxias do Sul since 2003 with positive results reported by the students, both beginners and seniors. T&D-Bench is available as an open source and platform-independent framework on the Internet.

The ubiquity of complex devices built on systems on chip (SoC) with multiple processor cores poses new challenges for developers of embedded systems. New development tools specifically designed for complex systems on chip can help solve them, but these tools are usually limited by the functionality of debugging support tools. High-quality debugging support with advanced features is necessary to take full advantage of complex SoC devices while reducing development time. The article discusses various mechanisms and ways to implement support for debugging systems on chip designed for complex real-time systems used, for example, in the Internet of Things (IoT) paradigm. This review includes an assessment of the available solutions and their suitability for use with the next generation of complex systems on chip with multiple processor cores. It is shown that many existing solutions do not allow developers to easily take advantage of complex functions integrated into the next-generation SoC. The basic debugging support functions for multicore SoCs are summarized and discussed. Recommendations are given for SoC develo­pers and for the future direction of research in this area in order to provide a more suitable basis for new development tools. Such tools are extremely necessary for all embedded hard real-time systems and are of high importance for minimizing the complexity of their development. Modern systems and devices implementing the Internet of Things paradigm are increasingly required to have sufficiently high real-time performance while maintaining low power consumption. These requirements lead to the cre­ation of multicore SoC solutions with support for a wide range of peripheral devices and communication protocols. The systems are limited by the requirements for working in harsh conditions, such as, for example, in the engine compart­ment of a car or on a radar tower. The development of embedded hard real-time systems, in which a task that fails to be completed on time can lead to physical damage of the device, is a complex process. Effective tools, such as interactive debuggers and profilers, are an integral part of solving these problems and are vital for developing reliable embedded systems. Modern technologies now allow the integration of the entire system on a single silicon chip, known as a system on a chip (SoC), which leads to the relocation of existing external interfaces, widely used for development purposes, to the chip. Traditionally, communication within an embedded system is carried out using an external processor system bus, which is implemented in the form of tracks on a printed circuit board. The printed circuit board must support the appropriate interfaces of development tools that require a physical connection, such as, for example, logic analyzers and oscilloscopes. Previously, placing exter­nal interfaces on a chip left fewer options for external analysis tools and, in fact, makes developers "blind" to the internal state of the SoC. Without a reliable and consistent representation of the state of the embedded system, the detection of defects or errors in the system may become difficult or even impossible. The main solution to the problem of the lack of external interfaces is to provide access to internal nodes from outside the system through existing interfaces. There are many different approaches to achieving the required visibility, and they are outlined in this review.

We have developed the 90 nm TEG (Test Element Group) that has large-scale patterns which compare well to those of a SoC(system on a chip) and has 4-corner address decoders. This TEG is based on the design rules of processes that are independent of the products. We have successfully measured process yield, failure terms, failure locations and evaluated characteristic variation in a chip. The yield of the first developed 130 nm large-scale TEG was improved successfully at this 90 nm TEG, and measured results were compared to 130 nm TEG. Stress tests and the new trial to SI (signal integrity) evaluation were also implemented. Those challenges will make the lead to the new knowledge of yield, variation and SI. With use of the electrical dimension measurement, charge-up damage, and analysis database software, this TEG will lead to help for SoC designers, manufactures and a strategic 65 nm technology.

Complexity in System on a Chip (SoC) design is rapidly escalating with the advent of more advanced nodes and the ability to integrate 100's of cores on a single die. This highlights the need to understand the power consumption of the device in the early architectural phases of SoC design. The Power Analysis tooling, centered on Network on a chip, and developed as part of this project allows for quick iteration of power management topologies and tradeoffs in power management policies. The approach followed allows for successive iteration and composability of the solution as the design progresses and additional details become available. Flexibility is present in the system to assign both degree of uncertainty and replace the imprecise information with new information as the design process is completed.

While silicon scaling makes possible highly integrated SOCs for function rich electronic products, the efforts required to design such an SOC has increased more rapidly than the transistor complexity of the SOC itself. At the same time, market competitiveness continues to demand feature differentiation and short TTM (time-to-market) for the high volume electronic products. This paper describes the emerging methodology of using configurable processors as the building blocks for complex SOC designs. Using processors to replace hardwired logic to accelerate hardware design and bring full chip-level programmability. Using configurability to deliver domain-specific efficiency, high throughput, low cost and low power dissipation. Configurable processor technology has made the creation and adoption of these tuned processors easy. Configurable processors have been used in a variety of high volume SOC platforms and adopted by market leaders. This paper also includes product examples.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC the design verification is a challenge for the system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here we present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on POF model. On average, the size, of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.

LDPC codes have recently received a lot of attention by their excellent error-correcting capability and have been adopted as an optional error correct coding scheme in WiMAX (802.16e) standard for mobility. In order to the low-complexity SOC (system-on-a-chip) design and multi-mode transmitter compatible, we proposed a novel application of LDPC decoder to substitute Viterbi decoder for convolutional encoder. The main character presented in this study is that the general two-decoder structure is replaced by one decoder. Our results indicate that the proposed scheme processes nice performance for mobile WiMAX system