System‐on‐a‐chip design platform with microcomputer co‐debugging interface

With the improvement of integration degree, more and more systems that originally implemented on PCB board are integrated into one chip, becoming a SOC (system on a chip). Also with the increasing demand for programmable performance, the use of multi microprocessors structure in SOC designs is becoming much more popular. For the complex real-time systems such as HDTV decoder, it is generally easier with multiple CPUs to provide instant response time and meet the demand of real-time and function complexity. In this paper, based on introduction of the HDTV SOC architecture we designed, a communication and control scheme between master-slave mode dual-processors in the SOC is proposed, as well as a shared memory control method among multi IP function modules in the SOC.

The demands for new embedded system products that provide new functionality are booming. The system on chip (SoC) technologies enables further cost, feature size reduction and makes embedded system product much more affordable accordingly. However, the software development for SoC product pushes the challenge further in reducing time to market. We propose a framework approach for embedded SoC software development that would (a) enable the parallel development in hardware and software, and (b) provide software framework for cross platform software reuse. Our approach is based on a tunable embedded software development platform (TESDP) that integrates an embedded software framework (ESF) and a simulated hardware framework (SHF). ESF provides a set real-time software frameworks that support cross platform reuse. SHF helps in decoupling the hardware and software development and enable the parallel development in software development parallel with the SoC hardware development. We demonstrate the feasibility of the TESDP approach with the development of a car-borne modular mobile data terminal (MMDT). MMDT provides data communication and global positioning capability for applications in the cargo truck fleet dispatching and monitoring. MMDT can also be applied in the domain related to intelligent transportation system (ITS).

We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

We present T&D-Bench, Teaching and Design Workbench, a framework for design space exploration of embedded processors. Design space exploration has become a fundamental phase of the SOC (System on a Chip) design process in industry and in research, and so it is important also in Computer Architecture education. T&D-Bench is an innovative framework to be employed in Computer Architecture education, providing the students a contact with a contemporary hardware design activity, and offering an easy and rapid design process, together with graphical user interface resources for tracking and steering the experiments with the processor models. T&D-Bench has been used at Universidade de Caxias do Sul since 2003 with positive results reported by the students, both beginners and seniors. T&D-Bench is available as an open source and platform-independent framework on the Internet.

: This report presents the design and development of a robotic tentacle manipulator research platform as a tool to explore new methods of enhancing the capabilities of remotely operated manipulators, autonomous manipulation, and autonomous search. We review the current state of dexterous manipulators and past milestones, choose manipulator morphology based on this review, and evaluate the morphology on the basis of design, control, and manufacturing constraints. A feasible architecture for a robotic tentacle manipulator research platform is conceived, designed, and built. Design and development of software, hardware, and mechanical components is presented. Applications of the robotic tentacle manipulator in autonomous robots are investigated. Potential effects of various design decisions are evaluated and strategies for platform improvements are suggested.

Embedded systems are increasingly synthesized today as systems-on-a-chip (SOCs), wherein existing functional blocks (also called cores) are used to implement different functions in the system specification. Emphasis during system synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a postprocessing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, performing test modifications after the SOC design has been optimized for target design constraints does not preserve the optimality of the solution obtained. In this paper, the authors present the first system-level synthesis for testability framework that integrates testability considerations into the synthesis process. Their work incorporates finite-state automata (FSA)-based symbolic testability analysis within the framework of an existing multiobjective optimization-based system synthesis tool to provide a viable solution. The experimental results show that the use of FSA-based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. System synthesis through the integrated framework for a number of examples indicates that efficient SOC architectures, which tradeoff different architectural features such as integrated circuit price, power consumption, and area under real-time constraints, can now be easily generated with low testability costs.

Motion estimation algorithm plays a crucial role in video coding/processing and accounts for almost one quarter of the gate count or area in many digital video system-on-a-chip (SoC) due to its computational intensive nature. In this paper, we present a complexity-reduced three dimensional (3D) motion estimator (ME) which reduces the number of search candidates and hence gate count significantly. Moreover, by virtue of its recursive architecture, hardware estimated sum of absolute differences (SAD) and motion vectors (MV) can be passed backed to the embedded DSP processor for image segmentation, resulting in efficient software/hardware partition in SoC designs. In addition, the calculated SAD's can also be further analyzed by the embedded CPU for rate control in video coding. Alleviating traditional ME artifacts such as illumination, this motion estimator with segmentation capabilities is readily applicable to video object planes (VOP) processing in levels higher than the advance simple profile in MPEG4, H.264 and motion compensated format converters such as deinterlacers and scan-rate converters.

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore’s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA platforms. While enabling the easy construction of heterogeneous systems, the approach has to face a major hurdle: by blurring the line between software and hardware development, it forces software developers to consider hardware limitations. This can be difficult through the abstractions that OpenMP introduces over the generated hardware. The high level synthesis tools used by OpenMP compilers to generate hardware already offer predictions on hardware usage. Their value for OpenMP offloading however is questionable. This paper is based on the data mining we conducted on thousands of kernel variations. It demonstrates and proves under which circumstances these predictions can be trusted in the context of OpenMP to FPGA offloading and concludes by showing how to derive runtime performance predictions from them. The model we present can be used without experience in hardware development and quickly predicts runtime on our benchmarks with an average Pearson correlation of 0.897. This knowledge allows developers to make fast, informed design decisions.KeywordsFPGAOpenMPtarget offloadingdata mining

The previous chapters described the basic principles for the application channel coding. Before proceeding to advanced channel coding techniques and its possible hardware realization we will introduce in this chapter the basic steps for a hardware design. An entire receiver is large system and comprises many different functionalities. Combining all of them on a single die yields a so called System-on-a-Chip (SoC). The SoC design requires the knowledge from system specification down to hardware partitioning and refinement. However, every SoC is partitioned in smaller functional blocks which can then be developed individually on component level. This is especially true for the channel decoder which is just one single component in a larger system. The same hold for e.g. demodulator, source encoder or decoder and so on. The advantage of designing components individually is that typically the functionality is restricted and can be well described. In this chapter we first revise (Sect. 4.1) the design flow for a single component and show the different design constraints which are posed either by the communications domain or the hardware domain. Note, that the design flow shown here is no general hardware design flow. It is restricted to communications specific constraints with respect to the introduced base band processing components. Memories are an extremely important part for the entire SoC and for each individual component as well.

Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device. The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications. The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance. In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.

In this paper, we propose a System-on-Chip (SoC) architecture that provides a high-flexibility system in a rapid development time. It is called Hybrid Multi SoC (H-MSoC). H-MSoC provides flexible SoC architecture that is easy to configure for physical and application layers development. These two aspects (physical and application layers) are dynamically designed and modified, hence it is important to consider and optimize their design methodology to support rapid SoC development. Physical layer development refers to Intellectual Property (IP) cores or hardware developments, while application layer development refers to user and interface application developments. H-MSoC is established from multi-SoC architectures which each SoC is localized and specified based on its development layer, either physical or application (hybrid). Physical layer development SoC is called Physical-SoC (Phy-SoC) and application layer development SoC is called Application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via ethernet. Ethernet is chosen because of its flexibility, high-speed, and easiness for configuration. For prototyping purpose, we used LEON3 SoC as Phy-SoC and ZYNQ-7000 SoC as App-SoC. Proposed design has been proved in real time testing and achieved good performance.

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP).Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source of the performance bottlenecks. The arbiter plays a very important role to manage the resource sharing on the SOC platform. This paper presents a reconfigurable arbiter with various combinations of arbitration algorithms. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys Design Complier with a TSMC 0.18 μm cell library. In addition, the power analysis of the reconfigurable arbiter at various arbitration states is reported. Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to market, thus how to verify IP functionality on bus protocol is challenge. Traditional simulation-based bus protocol monitor scan check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule based bus protocol checker, it contain ns 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently Keywords: Arbiter, Reconfigurable, System-on-chip, Arbitration Algorithm, FPGA, AMBA