An improved AVPG algorithm for SoC design verification using port order fault model

Summary form only given: Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of device-parameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.

With the improvement of integration degree, more and more systems that originally implemented on PCB board are integrated into one chip, becoming a SOC (system on a chip). Also with the increasing demand for programmable performance, the use of multi microprocessors structure in SOC designs is becoming much more popular. For the complex real-time systems such as HDTV decoder, it is generally easier with multiple CPUs to provide instant response time and meet the demand of real-time and function complexity. In this paper, based on introduction of the HDTV SOC architecture we designed, a communication and control scheme between master-slave mode dual-processors in the SOC is proposed, as well as a shared memory control method among multi IP function modules in the SOC.

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage.

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.

This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed errors. The fault model allocation phase associates a set of fault models on each suspected line. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

This paper presents a System on a Chip (SoC) Field-Programmable Gate Array (FPGA) implementation for Media Access Control (MAC) layer of a fast industrial Wireless Local Area Network (iWLAN) protocol, which is used to control industrial robots in factory automation environments. This protocol is a potential technique for industrial wireless communication system by using the Low overhead Packet Division Multiple Access (PDMA) scheme controlled by MAC layer. In our previous research, the MAC layer hardware was implemented and tested on simulation software, but the SoC design for the MAC layer has not been implemented and real tested on the FPGA. In this paper, we have successfully implemented the SoC system for MAC layer of this high-speed wireless communication protocol on the FPGA.

To heighten the biometrics security level, the biometrics feature extraction and verification need to be performed within smart cards, not in external card readers. However, the smart card chip has very limited processing capability, and typical fingerprint feature extraction and verification algorithms may not be executed on a state-of-the-art smart card. Therefore, this paper presents a system-on-chip (SoC) implementation of the fingerprint feature extraction algorithm which can be integrated into smart cards. To implement the ridge-following algorithm onto the resource-constrained SoCs, the algorithm has been modified to increase the efficiency of the hardware. Each functional block of the algorithm has been implemented in hardware or in software by considering its computational complexity, cost and utilization of the hardware, and efficiency of the entire system. The proposed system operated in 50MHz, and 20~50 minutiae could be extracted from typical 248timestimes292 fingerprint images in real time with our small area implementation (97K gates). Our current implementation developed as an IP for SoCs targeted for ARM CPU and AMBA bus can also be extended for many other smart card configurations

We present a hardware/software RTOS (real-time operating systems) generation framework for system-on-a-chip (SoC) applications. We claim that current SoC designs tend to ignore the RTOS until late in the SoC design phase. In contrast, we propose RTOS/SoC codesign where both the multiprocessor SoC architecture and a custom RTOS (with part potentially in hardware) are designed together. Thus, this paper introduces a hardware/software RTOS generation framework for customized design of an RTOS within specific predefined RTOS services and capabilities available in software and/or hardware (depending on the service or capability).

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.

While silicon scaling makes possible highly integrated SOCs for function rich electronic products, the efforts required to design such an SOC has increased more rapidly than the transistor complexity of the SOC itself. At the same time, market competitiveness continues to demand feature differentiation and short TTM (time-to-market) for the high volume electronic products. This paper describes the emerging methodology of using configurable processors as the building blocks for complex SOC designs. Using processors to replace hardwired logic to accelerate hardware design and bring full chip-level programmability. Using configurability to deliver domain-specific efficiency, high throughput, low cost and low power dissipation. Configurable processor technology has made the creation and adoption of these tuned processors easy. Configurable processors have been used in a variety of high volume SOC platforms and adopted by market leaders. This paper also includes product examples.

We have developed the 90 nm TEG (Test Element Group) that has large-scale patterns which compare well to those of a SoC(system on a chip) and has 4-corner address decoders. This TEG is based on the design rules of processes that are independent of the products. We have successfully measured process yield, failure terms, failure locations and evaluated characteristic variation in a chip. The yield of the first developed 130 nm large-scale TEG was improved successfully at this 90 nm TEG, and measured results were compared to 130 nm TEG. Stress tests and the new trial to SI (signal integrity) evaluation were also implemented. Those challenges will make the lead to the new knowledge of yield, variation and SI. With use of the electrical dimension measurement, charge-up damage, and analysis database software, this TEG will lead to help for SoC designers, manufactures and a strategic 65 nm technology.

Complexity in System on a Chip (SoC) design is rapidly escalating with the advent of more advanced nodes and the ability to integrate 100's of cores on a single die. This highlights the need to understand the power consumption of the device in the early architectural phases of SoC design. The Power Analysis tooling, centered on Network on a chip, and developed as part of this project allows for quick iteration of power management topologies and tradeoffs in power management policies. The approach followed allows for successive iteration and composability of the solution as the design progresses and additional details become available. Flexibility is present in the system to assign both degree of uncertainty and replace the imprecise information with new information as the design process is completed.

This paper describes RaceCheck, a new verification program that audits System-on-Chip (SoC) designs for race logic design errors. The unique features of RaceCheck are: it can perform both static and dynamic analysis to reveal hard-to-detect race logic, and it makes use of SoC designs' structural and timing information to suppress false violations. The static race logic analysis is testbench independent, and can be used in all stages of a SoC development. The dynamic race logic analysis uses an event-driven simulation kernel to execute a SoC operations, and reports the exact times, locations and frequency of occurrences of all detected race logic in the design. RaceCheck complements traditional design verification tools to aid users achieve 100 % functional coverage of their new SoC products and time-to-market

Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.