Configurable processor the building block for SOC (system-on-a-chip)

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology In particular, networks that span multiple chips will become important in the near future. We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the /Ethereal design flow the extended architecture was designed, implemented, and verified in 12 person months. To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitative results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost

System on chip (SOC) has emerged to be one of the major components to reduce the cost of final product recently. When the SOC chip first entered the market 10 years back, despite a single chip solution, was in fact more expensive than the solution with multiple chips due to larger die area and bad yield. The technology development continually break through has created an opportunity to allow even more transistors to be packed in a chip with lesser die area and better yield. This prompted for cost effective product no choice but back to SOC single chip solution. However, just SOC chip solution is not enough to further reduce BOM cost as this type of chip could be very complex with large pin count. The customer has constantly demanded a low cost system solution regardless whether it is SOC chip. IC Design Company is no longer a semiconductor IC chip provider; it has to deliver system solution in order to secure customers. To help customers reduce cost, SOC, is inevitable to be one of the cost effective components as it greatly reduce the PCB size and thus the cost. However, In today consumer market, this is still not enough, lower cost effort has to be continued in order to cut the cost to satisfy the demanding consumers hungry for cheap and quality product. This paper studies the low cost approach for the SOC application.

This paper presents a detailed analysis of an architectural pipeline scheme for Quantum-dot Cellular Automata (QCA); this scheme utilizes the so-called Bennett clocking for attaining high throughput and low power dissipation. In this arrangement, computation stages (utilizing Bennett clocking) and memory stages combine the low power dissipation of reversible computing with the high throughput feature of a pipeline. An example of the application of the proposed scheme to an XOR tree circuit (parity generator) is presented; a detailed analysis of throughput and power consumption is provided to show the effectiveness of the proposed architectural solution for QCA.

The main objective of paper is to design and implement a high speed processing system with high throughput and low complexity. We are using system on chip using AMBA bus. This high speed processing system is application specific. This system will be used for landmine detection during wars as high speed processing is need of application. Firstly input processor will be designed as per the application. Then the concurrent processor will be designed. VHDL coding of the entire system on chip will be done. The simulation will be performed using Xilinx and FPGA. After the processing system is designed it will be compared to the conventional controller system. Thus proving that the system on chip is efficient and fast processing than the controller system.

As a concept, “System in Package” or “SiP” relates to the objective of merging many or all of the electronic requirements of a functional system or a subsystem into one package. It is a concept that can at once be understood by people familiar with electronics and packaging yet is very difficult to define in absolute terms. Amkor uses the following attributes to define SiPs: Includes chip-level interconnect technology. In other words flip chip, wirebond, TAB, or other interconnect directly to an IC chip. This distinguishes small SMT board assemblies from being considered SiPs. More often than not, the SiP is small in physical size. Quite often includes passive components. The passives can be either surface mounted discrete components or can be embedded into or manufactured on the substrate material. Typically includes more than one IC chip. May include other components necessary to bring the SiP to a more complete functional system or subsystem level – such as housings, lids, RF shields, connectors, antennas, batteries, etc Quite often the term System-in-Package is used to describe multi-chip IC packages such as stacked die CSPs or MCM-PBGAs. The real power of SiP technology lies in its ability to integrate not only multiple ICs but also other components such as passives, connectors, antennas and so on into the package in order to create fully functional subsystems. System in Package has a parallel in the often-discussed System on Chip (SoC) methodology. While SoC has many good attributes, and has been the focus of several IC manufacturers for several years, by its very nature it is limited by what can be achieved within one wafer process. It is quite easy to understand that SoC may be limited in the type of IC functions that one would like to design into a system – or at best performance will likely be compromised due to a common wafer process. SiP is not limited by the constraint of a common wafer process, so that IC chips, each optimally suited for its function by both design and wafer fab process, can be easily combined together in one package (for example a CMOS digital IC with a GaAs HBT RF IC). There are several reasons why the market demand seems to be growing strongly for SiP solutions. These include: Size: The size of sub-system can be reduced by integrating multiple ICs and other components in an SiP Time to market: It is often faster combine ICs in an SiP than it is to implement SoC at the IC level. It is also faster to make changes to the system at the SiP level than to change the entire mask set of an SOC solution. SIP implementation is faster than tune & debug at system board level, especially in RF applications, (e.g. cell phones) SiP solutions reduce the complexity of the motherboard by moving the routing complexity to the package substrate. This often results in reduced layer count in the motherboard and simplifies product design. Performance advantages: – e.g. ASIC or CPU to memory data speed enhancements by combining the logic and memory chips close to one another in the SiP. Another example is power reduction by minimizing line lengths (capacitive loads) between IC's in a SiP. For RF & Wireless SiPs – the package is literally a part of the circuit and the package design and materials selection can have a great impact on whether the RF circuit functions as intended. Fully integrated “plug and play” SiP solutions enable system designers to implement additional functions, such as Bluetooth or camera modules, into a system with minimal design effort. Lower System Cost: An optimized SiP solution usually results in an overall system cost reduction compared to discrete IC packages. SiP enables the system designer to mix and match IC technology in order to optimize the performance of each functional block. Note that SoC and SiP are not mutually exclusive, but SiP offers more flexibility in IC partitioning to optimize performance and cost.

Over the past few decades, the microprocessor has emerged as a fixed, stand-alone, reusable block created by highly skilled specialists. Because developing good, efficient microprocessor architectures can take years, many designers have come to regard them as monolithic entities subject to change only over long time periods and after careful consideration by an anointed few. However, the rise of application-specific integrated circuit and system-on-chip (SoC) manufacturing technologies in the 1990s has laid the groundwork for a new, fourth era - that of post-RISC, configurable processors. Configurable processors enable system-on-chip designers to leverage the benefits of nanometer silicon lithography with relatively little manual effort. These processors can achieve much higher performance than processors with conventional fixed-instruction-set architectures through the addition of custom-tailored execution units, registers, and register files as well as specialized communication interface ports.

Compared with a sequence execution programs of commonly used processor, the configurable processor uses custom instructions and builds user data paths for a speedup of tens to hundreds of times aimed at special and critical programs in the algorithm. The real-time processing and display IR SoC (infrared System on Chip) based on custom instruction is realized by designing user logic function unit and data path of pseudo-color thermal image processing.

Cross talk is one of the major issues in ASCI design for recent technologies lesser than 180nm. It will make more complications in larger designs like System on Chip (SoC) and Network on Chip. Crosstalk noise affects the timing performance of the entire chip. It will degrade the signal which is passing from one module to another module in chip. In ASIC implementation, cross talk removal circuits required to remove cross talk and it will take extra area and power apart from the application. To avoid the crosstalk and delay, in proposed method we have introduced Bus Encoding Method (BEM) with low power dissipation with less area. In this paper, we designed 18T full adder circuit as testing sequence generator for crosstalk analysis. With the help of modified architecture, we can achieve crosstalk avoidance by low area, low power.

Many consumer embedded system products nowadays are built on platforms with System-On-a-Chip (SOC) in which two or more processor cores, which are not necessarily of the same type, are put into a single chip and form the architecture of Chip-level Multi-Processor (CMP). Although such platform is capable of achieving high performance at relatively low cost, the system architecture of CMP brings new challenges in system development and increases complexity in developing embedded software especially at the level of kernel or operating system. This paper presents our experience and some preliminary results from building a multi-kernel embedded system with high performance Inter-Process Communication (IPC) mechanism for application software running on the platform of a newly developed multi-core SOC, namely PAC Duo SOC, which is the latest product from the PAC (short for Parallel Architecture Core) Project implemented at Industry Technology Research Institute (ITRI) in Taiwan. PAC Duo SOC is a heterogeneous multi-processor SOC composed of one ARM926 core serving as the general purpose processor (GPP) and two ITRI PAC DSP cores serving as the special purpose processors (SPP). We ported Linux operating system to run on the ARM926 processor and ported the real-time kernel Micro-C/OS-II to run on one PAC DSP core, leaving the other PAC DSP core with the option of running either another Micro-C/OS-II or a different kernel. To address the issues in IPC, a high performance message-passing mechanism is developed. Its design not only takes application-specific requirements into account but also takes advantages of hardware features.

Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestion-free adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

The future of the autonomous cart follower system will be equipped with lots of sensory data, due to the ever lower cost of sensory devices. This provides design challenge on handling large data and firmware complexity. This paper investigates an alternative approach of running the autonomous cart follower system on neural network model using Field Programmable Gates Array (FPGA). A microcontroller based autonomous cart follower system is modified to use the FPGA board and implemented via the System on Chip (SOC) approach. The neural network model is trained off line then implemented as software code in the SOC. By observation the firmware footprint of the neural network model remains small size regardless of the neural network size. The result shows that with 40 % more additional resource utilization, the overall system improvement of 27 times is achieved with the usage of hardware acceleration block in SOC compared to SOC without hardware acceleration.

Self-repair replaces/bypasses faulty components in a system-on-chip (SoC) to keep the system functioning correctly even in the presence of permanent faults. Such faults may result from early-life failures, circuit aging, and manufacturing defects and variations. Unlike on-chip memories, processor cores, and networks-on-chip, little attention has been paid to self-repair of uncore components (e.g., cache controllers, memory controllers, and I/O controllers) that occupy significant portions of multi-core SoCs. In this paper, we present new techniques that utilize architectural features to achieve self-repair of uncore components while incurring low area, power, and performance costs. We demonstrate the effectiveness and practicality of our techniques, using the industrial OpenSPARC T2 SoC with 8 processor cores that support 64 hardware threads. Our key results are: 1. Our techniques enable effective self-repair of any single faulty uncore component with 7.5% post-layout chip-level area impact and 3% power impact. In contrast, existing redundancy techniques impose high (e.g., 16%) area costs. Our techniques do not incur any performance impact in fault-free systems. In the presence of a single faulty uncore component, there can be a 5% application performance impact. 2. Our techniques are capable of self-repairing multiple faulty uncore components without any additional area impact, but with graceful degradation of application performance. 3. Our techniques achieve high self-repair coverage of 97.5% in the presence of a single fault. Our self-repair techniques also enable flexible tradeoffs between self-repair coverage and area costs. For example, 75% self-repair coverage can be achieved with 3.2% post-layout chip-level area impact.

QNoC: QoS architecture and design process for network on chip

The growing demand for high-performance and energy-efficient memory has accelerated the development of low-power static random-access memory (SRAM) architectures, which form a critical component of modern system-on-chip (SoC) designs. This paper presents a comprehensive analysis of a novel 11T SRAM cell, with a strong emphasis on physical design considerations. The proposed 11T cell introduces a dedicated read line and a transmission gate in place of conventional pass transistors, resulting in enhanced read/write stability and reduced power consumption. The design is implemented and evaluated using Cadence Virtuoso with TSMC 65 nm CMOS technology. Simulation results confirm that the proposed 11T cell achieves 39.56% improved write static noise margin (SNM) and 11.50% lower power dissipation and 6.7% higher write speed compared to stack transistor-based 11T architecture. Additionally, a comparative analysis involving 6T, 8T, conventional 11T, and the proposed 11T SRAM cells was performed using both TSMC 65 nm and UMC 65 nm technology nodes. The results demonstrate that TSMC 65 nm technology yields superior performance over UMC. Post-layout simulations further validate the design’s stability in the presence of parasitic effects, with all evaluations conducted at a supply voltage of 1.2 V.

For getting more economy and smaller electronic products, technology of system in package (SiP) could complement the technology of system on a chip (SoC) perfectly. About SiP technology, we chose integral substrate technology to realize embedded passives, and used fine process such as high density interconnection (HDI) technology with a special dielectric material to achieve specific circuit functions. The special material is a high dielectric constant (Hi-DK; DK>40 @ 1GHz) material, which is suitable for Multi-Layer Printed Wiring Board (PWB) lamination process, and it was used to fulfill embedded capacitors. In the past years, we had utilized the technology to design Bluetooth/sup TM/ module, or other RF circuits. Furthermore, this technology is more economy than any other SiP processes, like Low Temperature Co-fired Ceramic (LTCC) substrate or silicon substrate, because it bases on the conventional PCB process. In this paper, we introduce not only the embedded capacitors but also some functional embedded passives in RF front-end circuits design on the Hi-DK organic substrate. Moreover, the RF front-end circuits include some functional passive elements: band pass filter, balun, and antenna, etc. Thus, in high frequency circuits, this kind organic substrate can reduce the module size, and in high-speed digital circuits, it also provides inexpensive decoupling capacitors. In the future, we will use this cost-effective technology to design analog and digital circuits on the same board, and the technology of SiP and SoC can be co-designed.