Advanced embedded memory testing: Reducing the defect per million level at lower test cost

The conference theme of ITC 2005 focuses on evolutionary as well as revolutionary trends in test technology. It states: "Recent advances in areas such as on-chip compression, low-cost test, and data analysis have burst onto the scene and are being rapidly and widely adopted". Indeed, test compression is one of the fastest adopted DFT methodologies. It had been researched for ten years before it was commercially introduced four years ago, and now it has become the mainstream DFT technology. Just a couple of years ago, before on-chip test compression was introduced, it was broadly believed that Logic BIST was going to be the next generation DFT methodology for manufacturing test. There were three main advantages of test compression over Logic BIST that contributed to its rapid adoption: simplicity of the design flow that does not require test points or x-bounding logic, excellent manageable and predictable test quality, and significant reduction of cost of test. Compression of volume of test data and test time by several orders of magnitude combined with on-chip PLLs controlling at-speed capture allow for dramatic reduction of cost of test. Disruptive technology of this magnitude has impact that goes far beyond cost of manufacturing test. Test compression has changed competitive landscape, opened up completely new opportunities in product quality and yield management, and has redefined DFT technology roadmaps. It stimulates research and development activities in new areas that until now were considered not promising or not practical, enables quality of testing that was unachievable until now, accelerates adoption of new fault models that take into account physical data bases and timing information, and changes how fault diagnostics and yield learning are done in manufacturing environment. The presentation will discuss many of these issues, new opportunities, new and not so new challenges, as well as future technology roadmaps.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments. For the 2017 Roadmap Cycle they are: automotive, consumer/office, medical, portable/wireless, Aerospace/Defense, high-end systems and IoT/Wearables. In addition, it forecasts the technical evolution associated with 21 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and previews expected highlights from 1 product and 2 technology areas from the 2017 iNEMI Roadmap inprocess work; the IoT/Wearable PEG and the Board Assembly and Optoelectronic technology TWG chapters. Examples of some timely information on forecast market trends and a section on “situation analysis” and expected challenges facing these technology areas over the ten year horizon of the roadmap will be shared. We will also share results of the “gap identification” that came out of the 2015 roadmap. The iNEMI Roadmaps are supported by as many as 15 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI has collaborated in the past is the ITRS (International Technology Roadmap For Semiconductors). The ITRS also developed a roadmap every two years and updated their tables every year. Their roadmap covered 15 different areas associated with semiconductor fabrication. The final ITRS2.0 Roadmap is being released June 30 and a new roadmap called the IRDS (International Roadmap For Devices & Systems) is replacing it. The new roadmap is planning to focus much more on “system” drivers. iNEMI collaborated closely with several of the technology groups within the ITRS and ITRS2.0 so the changes to both organizations is impactful. We are now working out the details of our collaborative process going forward. We are also collaborating with the IEEE CPMT Heterogeneous Integration roadmap to the extent that we have joint leadership for it and the iNEMI Packaging & Component Substrates Chapters. IPC, another of our collaborating organizations that has for years provided a chapter on Interconnect PCB (Organic) and continues to do so, has decided not to offer their larger roadmap this year thus concentrating their efforts on the iNEMI Roadmap. The roadmap scene is changing and evolving right along with the electronics industry.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments: automotive, consumer/office, medical, portable/wireless, and high-end systems as well as forecasting the technical evolution associated with about 20 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and highlights 2 product and 1 technology areas from the 2015 iNEMI Roadmap and resulting gap analysis work: Portable/Wireless and Automotive product sectors and the Organic Interconnect technology chapter. Examples of some tactical and more strategic gaps and needs mined from these chapters will be discussed. The iNEMI Roadmaps are supported by as many as 14 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI collaborates is the ITRS (International Technology Roadmap For Semiconductors). The ITRS develops a roadmap every two years and updates their tables every year. Their roadmap covers 15 different areas associated with semiconductor fabrication. Recently they have modified their approach to roadmapping semiconductor technology to focus much more on “system” drivers. iNEMI collaborates closely with several of the technology groups within the ITRS so the changes to both organizations is impactful. I will briefly discuss the changes within the ITRS and how they impact our collaborative work and the industry as well.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments: automotive, consumer/office, medical, portable/wireless, and high-end systems as well as forecasting the technical evolution associated with about 20 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and highlights 2 product and 1 technology areas from the 2015 iNEMI Roadmap and resulting gap analysis work: Portable/Wireless and Automotive product sectors and the Organic Interconnect technology chapter. Examples of some tactical and more strategic gaps and needs mined from these chapters will be discussed. The iNEMI Roadmaps are supported by as many as 14 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI collaborates is the ITRS (International Technology Roadmap For Semiconductors). The ITRS develops a roadmap every two years and updates their tables every year. Their roadmap covers 15 different areas associated with semiconductor fabrication. Recently they have modified their approach to roadmapping semiconductor technology to focus much more on system drivers. iNEMI collaborates closely with several of the technology groups within the ITRS so the changes to both organizations is impactful. I will briefly discuss the changes within the ITRS and how they impact our collaborative work and the industry as well.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.

This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed errors. The fault model allocation phase associates a set of fault models on each suspected line. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.

Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.

Nowadays System on Chip (SoC) is expected to perform a large number of applications as per the requirement of customers. Increase in the number of applications leads to an increase in the number of cores inside the SoC. Customers want to use a large number of applications in their product but in a cheap price. In this price competitive market, the manufacturer can not increase the price above a certain range in order to sustain in the market. It is decisive to have a high-quality product with the low price. Testing each core thoroughly can require high amount of time and increases the test economics. Hence it is better to cover significant faults only and test the cores partially. In this paper, we propose a method for incomplete testing of the SoC cores, which recedes Test Power (TP) and Test Data Volume (TDV). Our method persists significant fault coverage and tests most of the significant faults. We also propose a power aware Test access mechanism (TAM) architecture compatible with the reduced test vectors. It provides a trade-off between quality of product and testing parameters (i.e., TP, TDV). Results from experiments exhibit an effective reduction in TDV, TP with a nominal compromise on the quality of testing.

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC the design verification is a challenge for the system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here we present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on POF model. On average, the size, of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.

Ta–Si–C amorphous films thick were found applicable as a diffusion barrier against Cu penetration for sub- integrated circuit processing. The failure mechanisms of such a barrier were still unknown and were explored in this study. Ta–Si–C films were prepared by magnetron cosputtering using and C targets on p-type Si(100) substrate. Failure mechanisms were explored by Auger electron spectroscopy, X-ray diffraction, transmission electron microscopy, and four-point probe measurement on annealed films. In a sandwiched scheme , the failure temperatures 750 (18 atom % C) and (24 atom % C) were demonstrated. Deterioration of Ta–Si–C barriers arose from local nucleation of crystallites, providing short paths for copper penetration. Carbon addition significantly inhibited the formation of and increased the failure temperature of the barriers. From the understanding of the failure mechanism a possible solution is proposed to research thinner barriers (such as ) to meet the 2016 International Technology Roadmap for Semiconductors.

Smart sensors represent an attractive approach in sensor applications due to their adaptability, achieved by means of digital signal processing. Sensor adaptability can be further turned into a major advantage by introduction of smart calibration systems. Smart sensors are generally integrated with signal conditioning circuits. Signal conditioning circuits are needed to adjust the offset voltage and span, for compensation of temperature effects of both offset voltage and span, as well as to provide an appropriately amplified signal. The proposed approach is based on a special case of smart pressure sensors, but the developed calibration system is generally applicable for any kind of smart sensor. In manufacturing of modern electronic devices achieving and maintaining high yield level is a challenging task, depending primarily on the capability of identifying and correcting repetitive failure mechanisms. Yield enhancement is defined as the process of improving the baseline yield for a given technology generation from R&D yield level to mature yield. Yield enhancement is one of the strategic topics of ITRS (International Technology Roadmap for Semiconductors, Test And Test Equipment, 2006). This iterative improvement of yield is based on yield learning process, which is a collection and application of knowledge of manufacturing process in order to improve device yield through the identification and resolution of systematic and random manufacturing events (International Technology Roadmap for Semiconductors, Yield Enhancement, 2006). Yield improvement process will consequentially increase the number of test parameters and hence the calibration system complexity. One of advantages of increasing system complexity is the ability to integrate the input testing processes and output final testing processes into the calibration process itself, thus shortening the total time for calibration. Several types of smart sensors with integrated signal conditioning have been presented over the past few years (Takashima et al., 1997) & (IEEE Std. 1451.2 D3.05, 1997). The calibration processes and temperature compensating methods for these sensors are based either on analog, digital or mixed approaches. Analog approach usually comprises an amplifier with laser trimmable thin film resistors (Chau et al., 1997) & (Wang et al., 2005) or off-chip trimmable potentiometers (Schnatz et al., 1992) & (Lee et al., 1999), to calibrate the sensor span and offset voltage and to compensate for their temperature drift. Analog compensation

As more and more peripherals are integrated in System-On-Chip (SoC), the production testing cost per device is increasing sharply, which is eating up the gross margin of the product significantly. This paper proposes an alternate scheme for production testing whereby major part of the SoC testing can be done with a pre-tested and pre-verified custom made SoC. It will help to minimize the dependencies of Automatic Test Equipment (ATE) for SoC testing in production significantly. Hence production testing cost per device will be reduced. Also this scheme will enable to test many of the functional features of SoC on silicon, which were not possible to test using ATE due to high test cost. In this paper the micro architectural details of the scheme, system requirements, design challenges and case study conducted on different SoCs are presented. And the impact of this approach is also discussed.