Roadmapping the Electronics Manufacturing Supply Chain Takes a “Village”

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments: automotive, consumer/office, medical, portable/wireless, and high-end systems as well as forecasting the technical evolution associated with about 20 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and highlights 2 product and 1 technology areas from the 2015 iNEMI Roadmap and resulting gap analysis work: Portable/Wireless and Automotive product sectors and the Organic Interconnect technology chapter. Examples of some tactical and more strategic gaps and needs mined from these chapters will be discussed. The iNEMI Roadmaps are supported by as many as 14 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI collaborates is the ITRS (International Technology Roadmap For Semiconductors). The ITRS develops a roadmap every two years and updates their tables every year. Their roadmap covers 15 different areas associated with semiconductor fabrication. Recently they have modified their approach to roadmapping semiconductor technology to focus much more on system drivers. iNEMI collaborates closely with several of the technology groups within the ITRS so the changes to both organizations is impactful. I will briefly discuss the changes within the ITRS and how they impact our collaborative work and the industry as well.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments. For the 2017 Roadmap Cycle they are: automotive, consumer/office, medical, portable/wireless, Aerospace/Defense, high-end systems and IoT/Wearables. In addition, it forecasts the technical evolution associated with 21 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and previews expected highlights from 1 product and 2 technology areas from the 2017 iNEMI Roadmap inprocess work; the IoT/Wearable PEG and the Board Assembly and Optoelectronic technology TWG chapters. Examples of some timely information on forecast market trends and a section on “situation analysis” and expected challenges facing these technology areas over the ten year horizon of the roadmap will be shared. We will also share results of the “gap identification” that came out of the 2015 roadmap. The iNEMI Roadmaps are supported by as many as 15 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI has collaborated in the past is the ITRS (International Technology Roadmap For Semiconductors). The ITRS also developed a roadmap every two years and updated their tables every year. Their roadmap covered 15 different areas associated with semiconductor fabrication. The final ITRS2.0 Roadmap is being released June 30 and a new roadmap called the IRDS (International Roadmap For Devices & Systems) is replacing it. The new roadmap is planning to focus much more on “system” drivers. iNEMI collaborated closely with several of the technology groups within the ITRS and ITRS2.0 so the changes to both organizations is impactful. We are now working out the details of our collaborative process going forward. We are also collaborating with the IEEE CPMT Heterogeneous Integration roadmap to the extent that we have joint leadership for it and the iNEMI Packaging & Component Substrates Chapters. IPC, another of our collaborating organizations that has for years provided a chapter on Interconnect PCB (Organic) and continues to do so, has decided not to offer their larger roadmap this year thus concentrating their efforts on the iNEMI Roadmap. The roadmap scene is changing and evolving right along with the electronics industry.

iNEMI (International Electronics Manufacturing Initiative) and the ITRS (International Technology Roadmap for Semiconductors) have been collaborating for the past several roadmap cycles to the extent that the iNEMI “Portable/Consumer Chapter” has provided input to the “ITRS Drivers” Chapter and two chapters from each roadmap share their leadership: 1. Packaging & Component Substrates/ Assembly & Packaging 2. MEMS & Sensors/MEMS. The iNEMI Roadmap also uses a version of the ITRS Executive Overview as the Semiconductor Technology Chapter. The individual roadmaps also refer to each other when applicable in their respective chapters. Starting with the last two cycles the two roadmap groups have been working together to develop a process for collaborating on the “More than Moore” aspects of the roadmaps. Discussions and presentations at various ITRS meeting venues led to a workshop held in Lyon, France in 2013 (in conjunction with the ITRS Spring Meeting) co-hosted by the European contingent of the ITRS More than Moore cross-TWG study group and iNEMI to work on this process. A follow-up meeting was held the following July (as a part of the ITRS Summer Meeting) at Stanford University and hosted by Paolo Gargini, ITRS Chairman, Patrick Cogez, ITRS cross TWG study group and Chuck Richardson, iNEMI Roadmap Director. There are plans to continue this roadmap cycle (2013 major upgrade for ITRS) and 2015 update for the iNEMI Roadmap as we have been doing for the past several cycles while continuing to work out a process to expand the collaboration to “More than Moore”.This paper will address the approach and request feedback from attendees as to how best to proceed.

The continuous scaling of CMOS devices according to Moore’s law has brought the design complexity in terms of number of transistors and performance requirements to an extremely high level. Design styles and methods need constant adaptation in order to manage this growing complexity and to enable full exploitation of the potentials of advanced CMOS technologies. A prediction of these potentials was presented in the International Technology Roadmap for Semiconductors (ITRS) [38], created by the Semiconductor Industrial Association (SIA). The final ITRS roadmap update was in 2013. Because of the changing semiconductor markets, from computer and consumer to mobile, automotive and IoT, the Semiconductor Industrial Association decided to change the focus of the ITRS towards seven topics and continued with an ITRS 2.0 version. With the end of Moore’s Law at the horizon, ITRS 2016 has become the final roadmap and will be replaced by a new initiative, named the International Roadmap for Devices and Systems (IRDS), which now also include beyond CMOS or more than Moore devices.

Atomic force microscopy (AFM) is an important technique for measurement of the surface roughness and surface features of high technology surfaces such as semiconductor chips and micro-optics. One of the key measurands is the linewidth of semiconductor features [1]. A class of AFM instruments often called CD-AFM has been developed for the purpose of measuring linewidth accurately (Fig. 9.1). The smallest linewidth or hole diameter on a semiconductor circuit is called the critical dimension or CD. Recently, a requirement has arisen in the semiconductor industry for control, specification, and measurement of line edge roughness (LER) for functional semiconductor features, such as processor gates [2–5]. As feature dimensions become steadily smaller, the LER of a single gate is becoming a significant fraction of the gate length itself. Hence, the LER is expected to have a significant effect on properties of the gate such as leakage current. The International Technology Roadmap for Semiconductors (ITRS) [6] specifies a physical gate length for 2002 of 75 nm and a maximum LER of 3.9 nm. The effect of LER on the function of an electronic gate has been modeled by several studies and these models have been verified experimentally. This work has led in part to a succinct specification of LER requirements for current and future generations of semiconductor circuits. This specification has been inserted into the International Technology Roadmap for Semiconductors (ITRS) [6].KeywordsAtomic Force MicroscopyLine StructureSpatial WavelengthSidewall RoughnessAtomic Force Microscopy CharacterizationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Smart sensors represent an attractive approach in sensor applications due to their adaptability, achieved by means of digital signal processing. Sensor adaptability can be further turned into a major advantage by introduction of smart calibration systems. Smart sensors are generally integrated with signal conditioning circuits. Signal conditioning circuits are needed to adjust the offset voltage and span, for compensation of temperature effects of both offset voltage and span, as well as to provide an appropriately amplified signal. The proposed approach is based on a special case of smart pressure sensors, but the developed calibration system is generally applicable for any kind of smart sensor. In manufacturing of modern electronic devices achieving and maintaining high yield level is a challenging task, depending primarily on the capability of identifying and correcting repetitive failure mechanisms. Yield enhancement is defined as the process of improving the baseline yield for a given technology generation from R&D yield level to mature yield. Yield enhancement is one of the strategic topics of ITRS (International Technology Roadmap for Semiconductors, Test And Test Equipment, 2006). This iterative improvement of yield is based on yield learning process, which is a collection and application of knowledge of manufacturing process in order to improve device yield through the identification and resolution of systematic and random manufacturing events (International Technology Roadmap for Semiconductors, Yield Enhancement, 2006). Yield improvement process will consequentially increase the number of test parameters and hence the calibration system complexity. One of advantages of increasing system complexity is the ability to integrate the input testing processes and output final testing processes into the calibration process itself, thus shortening the total time for calibration. Several types of smart sensors with integrated signal conditioning have been presented over the past few years (Takashima et al., 1997) & (IEEE Std. 1451.2 D3.05, 1997). The calibration processes and temperature compensating methods for these sensors are based either on analog, digital or mixed approaches. Analog approach usually comprises an amplifier with laser trimmable thin film resistors (Chau et al., 1997) & (Wang et al., 2005) or off-chip trimmable potentiometers (Schnatz et al., 1992) & (Lee et al., 1999), to calibrate the sensor span and offset voltage and to compensate for their temperature drift. Analog compensation

Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.

In this paper, effects of expected physical limits of CMOS technology on the performance of small-scale System-on-Chips (SoCs) are described. The exponential progress of CMOS technology has entered to the saturation phase. This could be called, if we like, a third phase of the Moore's law. In this third phase of development, the peak-performance of SoCs is not any more in the main concern. Instead of that, we could see an explosion of creative small-size applications: bionic appendages, smartphones with smart sensors, networks of tiny sensors, and a host of other applications we have yet to imagine. The International Technology Roadmap for Semiconductors (ITRS) lists expected performance parameters for CMOS technology up to the year 2028. In this paper, it is shown that starting from the simple RTL architecture parameters, e.g., gate count, and using performance figures taken from ITRS, we are able to figure out the (space-time-energy) performance limits of CMOS implementation of any logic architecture. As a practical example, the study of performance limits of a novel digital receiver suitable to be used in different capillary networks of Internet-of-Things applications is described, here. Design space exploration technique described in this paper can be used to find out performance limits of wide range of smart object applications.

Dual material gate nanowire field effect diode (DMG-NWFED): Operating principle and properties

A key enabler to a successful process development and to the device functionality is the introduction of a proper metrology framework, consisting in the selection of the 'correct' tool class for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand. The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update. In order to investigate in deper details the actual status of each selected technique, a list of key characteristics was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy and 'Combo' approaches. Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node proces development are presented.

The International Technology Roadmap for Semiconductors (ITRS) provides the semiconductor industry with the timing of critical technology needs for future generations of integrated circuits. The Metrology roadmap in the ITRS describes the measurement needs based on the process requirements found in the Lithography, Front End Processes, Interconnect, and Packaging Roadmaps. This paper illustrates the impact of the Metrology Roadmap on the development of key measurement technology.

Motivated by the requirement of International Technology Roadmap for Semiconductors (ITRS), this article addresses ITRS modelling and simulation requirements particularly electromigration and thermomigration. The governing equations, material and damage mechanics models are discussed, finite element formulations are developed, and finally results from simulations and experiments are compared to validate simulation results.

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies.

The ultimate downsizing of the minimum feature size is hampered by physical, technological, and economical limitations. To ensure Moore’s law below 100 nm technology nodes both front- and back-end processing have to face technological challenges as clearly stipulated by the International Technology Roadmap for Semiconductors (ITRS). Lithography, gate stack, shallow junctions, high- and low-k dielectrics, and interconnect schemes are nowadays amongst the hot research issues leading to a global collaboration. This paper reviews some of the on-going research efforts to come to cost-effective solutions forming the backbone for future technology generations. Moreover the status and evolution of complementary metal oxide semiconductor (CMOS) compatible image sensors, infrared (IR) detectors, and of biosensors is treated.

For the successful implementation of extreme ultraviolet lithography (EUVL) technology for the future semiconductor fabrication process, EUV mask technology is considered to be one of the most critical issues. Since EUV light is strongly absorbed by most materials, reflective optics is applied to all the optical components, including the mask. As a result, the EUV mask structure, based on the mirror-type mask blank, is radically different from that of conventional optical lithography. All the mask components must be prepared with great care to consider the 13.5-nm reflection, which requires nano-scale thin-film technologies. The International Technology Road Map for Semiconductors (ITRS) forecasted that the target technology node for EUVL implementation would be 32 nm and below; today, mask defects are the leading challenge for EUV masks. The reflection of a 13.5-nm wavelength requires a multilayer (ML) structure consisting of many alternating layers of materials having dissimilar EUV optical constants. The Bragg reflection—constructive interference of the partially reflected beam at several interfaces—is the only principle to have EUV reflection, and its efficiency is determined by the structural factor (e.g., the thickness of each layer and their ratios) as well as optical properties (refractive index and extinction coefficient). To produce optical contrast for imaging, the patterns with high EUV absorbance should be formed on the top of this ML mirror. An oblique incident light angle, which is inevitable during image transfer with an EUVL system and causes a shadowing effect, imposes a unique restriction for the EUV mask structure. The ML and absorber specifications are specified in the standard SEMI P38-1103.