Microelectronics packaging technology roadmaps, assembly reliability, and prognostics

Fine-pitch ball grid array (BGA) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch plastic ball grid array (PBGA) packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the coefficient of thermal expansion (CTE) as measured by thermomechanical analyzer (TMA) typically starts to change at 10-15/spl deg/C lower temperature than the T/sub g/ specified by differential scanning calorimetry (DSC) potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125/spl deg/C. High T/sub g/ substrates with glass-transition temperatures much higher than the 125/spl deg/C high temperature limit, are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships were derived on ceramic ball grid array (CBGA) assemblies, with predominantly solder mask defined (SMD) pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than the non solder mask defined (NSMD) pads in thermal fatigue. The thermal mismatch on CBGAs is much larger than PBGA assemblies. Crack propagation in CBGAs is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15, 17, and 23mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-T/sub g/ printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of bis-maleimide triazine (BT) substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

This article provides a method to perform finite element analysis (FEA) and theoretical analysis on stress and strain characteristics of plastic ball grid array (PBGA) assembly under the random vibration environment. For the mixed solder joints, ball diameter, ball pitch and ball array were selected as three critical parameters. By using a L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sub> (3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ) orthogonal matrix, the mixed solder joints of PBGA components which have nine different technology parameter combinations were designed. In order to investigate the distribution of stress and strain of mixed solder joints, random vibration simulation for the PBGA assembles was simulated. Based on the stress value, range analysis was researched. The results indicate that the maximum stress of PBGA occurs at the outside corner of solder joints matrix and concentrates on the interface between the solder ball and pad near the PCB. In this study, the stress of mixed solder joints is affected by solder ball array, ball pitch, ball diameter in a descending order, and the maximum stress of the mixed solder joints is inversely proportional to all of them. The results lay a basis for high reliability design of PBGA assembly for engineering application.

A two-sided no clean mass reflow process for large plastic ball grid array (PBGA) and plastic quad flat pack (PQFP) packages is presented. Emphasis is placed on the PBGA and PQFP assembly parameters such as the design, materials, and processing of the packages and printed circuit board (PCB), solder paste, stencil printing, pick-and-place, reflow, and inspection. The solder joint reliability of the two-sided PCB assembly is evaluated by shear tests and thermal cycling tests.

The objective of this study is to experimentally and numerically investigate thermal and residual deformation of plastic ball grid array (PBGA) package and assembly. Shadow moire was used to measure their real-time out-of-plane deformations (warpages) during heating and cooling conditions. A finite element model with material properties characterized by dynamic mechanical analyzer and thermomechanical analyzer was established to simulate the thermally-induced deformations of test specimens for understanding mechanics. The full-field warpages of the PBGA package and assembly were measured during the temperature cycling. The results show that a maximum warpage with a concave (smiling) shape in both package and assembly occurred at the neighborhood of 155 degrees C during the thermal cycling, rather than with a convex (crying) shape at room temperature by assuming the warpage-free (or stress-free) temperature is at 175 degrees C of molding. This issue has been resolved through the finite element analyses by cooperating into the residual strain (stress) in the epoxy molding compound (EMC) of the package, which is obtained by measuring the residual and thermal deformations of the detached EMC/die bi-material structure. This residual strain of the EMC maybe comes either from the chemical shrinkage of the EMC curing, or possible from stress relaxation of the EMC during the first solder reflow of attaching the solder balls. Furthermore, the consistency of thermal deformations for both the package and assembly obtained from the finite element models indicates that the maximum warpage occurs at the corner of the substrate at near 155 degrees C, rather than at the room temperature, due to the glass transition temperature (Tg) and residual strains of the EMC. This maximum warpage can be mitigated by lowering the residual shrinkage strain. And the warpage of the PBGA assembly coincides with the package at the temperature beyond 155 degrees C (highly resulting from apparent creep of the solder balls), but is larger than that of the package below 155 degrees C, due to constraint of the printed circuit board through less-pronounced creep solder balls.

In the present study, a facility, i.e., a mechanical deflection system (MDS), was established and applied to assess the long-term reliability of the solder joints in plastic ball grid array (BGA) assembly. It was found that the MDS not only quickly assesses the long-term reliability of solder joints within days, but can also mimic similar failure mechanisms in accelerated thermal cycling (ATC) tests. Based on the MDS and ATC reliability experiments, the acceleration factors (AF) were obtained for different reliability testing conditions. Furthermore, by using the creep constitutive relation and fatigue life model developed in part I, a numerical approach was established for the purpose of virtual life prediction of solder joints. The simulation results were found to be in good agreement with the test results from the MDS. As a result, a new reliability assessment methodology was established as an alternative to ATC for the evaluation of long-term reliability of plastic BGA assembly.

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

The measure of package performance depends on the specific application. A high speed, high I/O application poses many restrictions on the required performance in terms of thermal management, reliability as well as electrical integrity. Electrical performance issues have become a very significant performance figure with the increasing circuit density and faster rise time contrary to the traditional view of a package. The drive towards higher chip I/O, reducing device dimensions and demand for lower inductance is forcing many to abandon the traditional chip bonding techniques such as wire-bonding and pursue flip-chip techniques (i.e,, C4). The chip carrying substrate facilitates the fanning-out of the I/Os, powering up the chip, and providing I/O interface to the next level. A host of substrate technologies are available, In this paper we look at the trade offs between PBGA (Plastic Ball Grid Array) and CBGA (Ceramic Ball Grid Array) solutions from an electrical performance, package design and application point of view.

This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments. For the 2017 Roadmap Cycle they are: automotive, consumer/office, medical, portable/wireless, Aerospace/Defense, high-end systems and IoT/Wearables. In addition, it forecasts the technical evolution associated with 21 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and previews expected highlights from 1 product and 2 technology areas from the 2017 iNEMI Roadmap inprocess work; the IoT/Wearable PEG and the Board Assembly and Optoelectronic technology TWG chapters. Examples of some timely information on forecast market trends and a section on “situation analysis” and expected challenges facing these technology areas over the ten year horizon of the roadmap will be shared. We will also share results of the “gap identification” that came out of the 2015 roadmap. The iNEMI Roadmaps are supported by as many as 15 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI has collaborated in the past is the ITRS (International Technology Roadmap For Semiconductors). The ITRS also developed a roadmap every two years and updated their tables every year. Their roadmap covered 15 different areas associated with semiconductor fabrication. The final ITRS2.0 Roadmap is being released June 30 and a new roadmap called the IRDS (International Roadmap For Devices &amp; Systems) is replacing it. The new roadmap is planning to focus much more on “system” drivers. iNEMI collaborated closely with several of the technology groups within the ITRS and ITRS2.0 so the changes to both organizations is impactful. We are now working out the details of our collaborative process going forward. We are also collaborating with the IEEE CPMT Heterogeneous Integration roadmap to the extent that we have joint leadership for it and the iNEMI Packaging &amp; Component Substrates Chapters. IPC, another of our collaborating organizations that has for years provided a chapter on Interconnect PCB (Organic) and continues to do so, has decided not to offer their larger roadmap this year thus concentrating their efforts on the iNEMI Roadmap. The roadmap scene is changing and evolving right along with the electronics industry.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments: automotive, consumer/office, medical, portable/wireless, and high-end systems as well as forecasting the technical evolution associated with about 20 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and highlights 2 product and 1 technology areas from the 2015 iNEMI Roadmap and resulting gap analysis work: Portable/Wireless and Automotive product sectors and the Organic Interconnect technology chapter. Examples of some tactical and more strategic gaps and needs mined from these chapters will be discussed. The iNEMI Roadmaps are supported by as many as 14 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI collaborates is the ITRS (International Technology Roadmap For Semiconductors). The ITRS develops a roadmap every two years and updates their tables every year. Their roadmap covers 15 different areas associated with semiconductor fabrication. Recently they have modified their approach to roadmapping semiconductor technology to focus much more on “system” drivers. iNEMI collaborates closely with several of the technology groups within the ITRS so the changes to both organizations is impactful. I will briefly discuss the changes within the ITRS and how they impact our collaborative work and the industry as well.

iNEMI released its 2015 Technology Roadmap to members on January 6, 2015 and to the industry for purchase on April 1st. Every two years iNEMI maps future manufacturing technology needs of the global electronics industry for the next ten years. It discusses the major business and technology issues, paradigm shifts, emerging technologies and markets, technology gaps, and identified needs in each of several product segments: automotive, consumer/office, medical, portable/wireless, and high-end systems as well as forecasting the technical evolution associated with about 20 different areas that support these product area needs. The resulting gaps identified between the product needs and technical capabilities form the basis for iNEMI projects and potential research programs within and outside iNEMI. This paper discusses the upcoming iNEMI 2017 roadmap process and highlights 2 product and 1 technology areas from the 2015 iNEMI Roadmap and resulting gap analysis work: Portable/Wireless and Automotive product sectors and the Organic Interconnect technology chapter. Examples of some tactical and more strategic gaps and needs mined from these chapters will be discussed. The iNEMI Roadmaps are supported by as many as 14 other organizations (including the SMTA) that provide help from recruiting their members to work on the roadmap, to providing completed chapters. One organization with whom iNEMI collaborates is the ITRS (International Technology Roadmap For Semiconductors). The ITRS develops a roadmap every two years and updates their tables every year. Their roadmap covers 15 different areas associated with semiconductor fabrication. Recently they have modified their approach to roadmapping semiconductor technology to focus much more on system drivers. iNEMI collaborates closely with several of the technology groups within the ITRS so the changes to both organizations is impactful. I will briefly discuss the changes within the ITRS and how they impact our collaborative work and the industry as well.

iNEMI (International Electronics Manufacturing Initiative) and the ITRS (International Technology Roadmap for Semiconductors) have been collaborating for the past several roadmap cycles to the extent that the iNEMI “Portable/Consumer Chapter” has provided input to the “ITRS Drivers” Chapter and two chapters from each roadmap share their leadership: 1. Packaging & Component Substrates/ Assembly & Packaging 2. MEMS & Sensors/MEMS. The iNEMI Roadmap also uses a version of the ITRS Executive Overview as the Semiconductor Technology Chapter. The individual roadmaps also refer to each other when applicable in their respective chapters. Starting with the last two cycles the two roadmap groups have been working together to develop a process for collaborating on the “More than Moore” aspects of the roadmaps. Discussions and presentations at various ITRS meeting venues led to a workshop held in Lyon, France in 2013 (in conjunction with the ITRS Spring Meeting) co-hosted by the European contingent of the ITRS More than Moore cross-TWG study group and iNEMI to work on this process. A follow-up meeting was held the following July (as a part of the ITRS Summer Meeting) at Stanford University and hosted by Paolo Gargini, ITRS Chairman, Patrick Cogez, ITRS cross TWG study group and Chuck Richardson, iNEMI Roadmap Director. There are plans to continue this roadmap cycle (2013 major upgrade for ITRS) and 2015 update for the iNEMI Roadmap as we have been doing for the past several cycles while continuing to work out a process to expand the collaboration to “More than Moore”.This paper will address the approach and request feedback from attendees as to how best to proceed.

Shadow Moire technique was used to study the out-of-plane displacements that represent warpage of advanced Plastic Ball Grid Array (PBGA) packages. Two types of PBGA packages, die-up and cavity-down configurations, were studied. The latter type is usually known as Enhanced Plastic Ball Grid Array (EPBGA) package due to the advantage it offers for thermal dissipation. Shadow Moire studies indicated that cavity-down package substrates warp in a concave configuration. Die-up package substrates warp in a convex configuration. Increase in temperatures up to 240/spl deg/C had an insignificant effect on the warpage of cavity-down substrates, whereas the die-up package substrate warpage improved with increasing temperature. However, the die-up substrates reverted to their original warpage upon cooling. The sum of the warpage and the ball diameter variation account for almost all the non-planarity. The packages with worse coplanarities showed invariably worse warpages. Substrate warpage of 4 mils or less is required for the successful assembly of PBGA packages. Since cavity-down packages do not show any improvement with increasing temperature, package non-planarity should be less than 7 mils by the seating plane method to ensure less than 4 mils of warpage. The assembly processes can tolerate higher levels of coplanarity for die-up packages as warpage improves at reflow temperatures. It is recommended that the coplanarity be measured by the seating plane method.

The continuous scaling of CMOS devices according to Moore’s law has brought the design complexity in terms of number of transistors and performance requirements to an extremely high level. Design styles and methods need constant adaptation in order to manage this growing complexity and to enable full exploitation of the potentials of advanced CMOS technologies. A prediction of these potentials was presented in the International Technology Roadmap for Semiconductors (ITRS) [38], created by the Semiconductor Industrial Association (SIA). The final ITRS roadmap update was in 2013. Because of the changing semiconductor markets, from computer and consumer to mobile, automotive and IoT, the Semiconductor Industrial Association decided to change the focus of the ITRS towards seven topics and continued with an ITRS 2.0 version. With the end of Moore’s Law at the horizon, ITRS 2016 has become the final roadmap and will be replaced by a new initiative, named the International Roadmap for Devices and Systems (IRDS), which now also include beyond CMOS or more than Moore devices.

The present study is carried out to characterise the ball shear strengths of ceramic ball grid array (CBGA) and plastic ball grid array (PBGA) packages with lead-free solder pastes. Three commercially available Sn/Ag/Cu (SAC) solder pastes such as Sn 96.5/Ag3.0/Cu0.5 and 95.5/Ag3.8/Cu0.7 with a no-clean flux are employed. The effects of temperature profiles during reflow on the strength of solder joints are studied. Their printing abilities are also observed. Of particular concern for ceramic ball grid array packages is the interaction between 90/10 Pb/Sn compound solder balls and SAC solder pastes. The composition of the solder paste region between the I/O pad and the solder ball is analysed using the energy dispersive X-ray (EDX) machine.