Euclidean Geometry-Based Spatially Coupled LDPC Codes for Storage

Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean geometry low-density parity-check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-18</sup> upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> bit/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead.

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

Low-density parity-check (LDPC) codes are promising for low code rate applications, however its competitiveness over BCH codes in the high code rate region is not well studied. In this work, we compare the Euclidean geometry (EG) LDPC and BCH codes of the length 1,023, 4,095, and 16,383 that have the code rates of 0.75~0.85. Hard-decision input data are applied to both decoders, and the EG-LDPC codes are decoded using the layered bit-flipping (BF) algorithm. Since the number of needed iterations for LDPC decoding depends on the channel condition, both decoders are designed to have the similar minimum throughput. Not only error performance but also hardware complexity and power consumption of these decoders are compared.

In this paper, we propose a concatenated code by combining a Recursive Systematic Convolutional (RSC) code with a Low-Density Parity-Check (LDPC) code. The proposed concatenated code is encoded in parallel by an RSC encoder and an LDPC encoder without interleavers between them. When decoding the proposed concatenated code, the information bits are decoded by two decoding algorithms, and soft information is exchanged between the RSC decoder and the LDPC decoder. This allows for the elimination of wrong codewords output by each decoder. The use of an LDPC code allows us to halt the decoding process when the valid codeword is obtained. We evaluate the error rate performance of the proposed concatenated code by computer simulations. We show that the proposed concatenated code does not have a high error floor, and achieves better BLock Error Rate (BLER) performance than either conventional LDPC codes or conventional turbo codes in the high Eb/No region. We also show that since the proposed concatenated code can correct wrong codewords output by each decoder, it achieves better BLER than the regular LDPC code at the same Bit Error Rate (BER).

As technology scales, memories have become more susceptible to radiation induced multiple bit upsets (MBUs). Multibit error correction codes (MECC) are an effective approach to mitigate MBUs in memories. This paper proposes a new codeword structure to protect memory against MBUs. Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed codeword to assure the reliability of memory with low redundancy overhead. Furthermore, the proposed codeword can protect some longer data which is difficult for other MECCs to deal with. By using the proposed codeword, both low redundancy overhead scheme and long data width scheme for multibit error correction are presented. Finally, the proposed schemes have been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed method has a superior protection level. Compared with general MECC, it has lower redundancy and performance overheads.

In mobile communications, the quality of signal is deteriorated by fading. The spatial diversity technique is used to reduce the degradation of the signal by fading. There are several techniques to realize the spatial diversity gain, such as Single- Input Multiple-Output (SIMO), Space-Time Block Code (STBC), and so on. The SIMO system realizes the receive diversity. The error correcting code can be combined with spatial diversity gain. Low-Density Parity Check (LDPC) codes can achieve good performance approaching Shannon limit. In particular, an irregular LDPC code with optimum degree distribution achieves better performance than a regular LDPC code. The optimum degree distribution of the irregular LDPC code depends both on the channel and the system. In this paper, we derive the Eb/No thresholds of a regular LDPC codes and the irregular LDPC codes for SIMO systems with several diversity orders. The Eb/No threshold is the smallest Eb/No that the decoder can achieve the error free. We also derive the optimum degree distributions of the irregular LDPC codes for SIMO systems with several diversity orders. We show that with low diversity order, the optimum degree distributions of the irregular LDPC code depends on the diversity order largely, while with high diversity order, the optimum degree distribution depends both on the diversity order and the combining scheme largely. We also show that comparing the optimum degree distributions for MRC and STBC, when the diversity orders are the same, the optimum degree distributions are also the same.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

Harvesting energy from radio frequency signals along with transmitting data through them is appealing for different wireless communication scenarios, such as radio frequency identification (RFID) systems and implantable devices. In this paper, we propose a technique to design nonlinear codes for the use in such systems taking into account both energy transmission and error rate requirements. In particular, we propose using concatenation of a nonlinear trellis code (NLTC) with an outer low-density parity-check (LDPC) code. We design the NLTC based on maximization of its free distance. We give necessary and sufficient conditions for its catastrophicity; in order to avoid catastrophic codes, we connect each designed NLTC to a corresponding linear convolutional code allowing for the use of simpler conditions for verification. Furthermore, we use EXIT charts to design the outer LDPC code while fixing the inner NLTC. Via examples, we demonstrate that our designed codes operate at ∼ 0.8 dB away from the information theoretic limits, and they outperform both regular LDPC codes and optimized irregular LDPC codes for additive white Gaussian noise (AWGN) channels. In addition, we show that the proposed scheme outperforms the reference schemes of concatenating LDPC codes with nonlinear memoryless mappers and using classical linear block codes in a time switching mode. © 2016 IEEE.

The replicate-and-mask (R&M) construction of finite-length spatially-coupled (SC) LDPC codes is proposed in this paper. The proposed R&M construction generalizes the conventional matrix unwrapping construction and contains it as a special case. The R&M construction of a class of algebraic spatially coupled (SC) quasi-cyclic (QC) LDPC codes over arbitrary finite fields is demonstrated. The girth, rank, and time-varying periodicity of the proposed R&M SC QC LDPC codes are analyzed. The error rate performance of finite-length nonbinary algebraic SC QC LDPC codes is investigated with window decoding. Compared to the conventional unwrapping construction, it is found through numerical simulations that the R&M construction resulted in SC QC LDPC codes with better block error rate performance and lower error floors. With a flooding schedule decoder, it is shown that the proposed R&M algebraic SC QC LDPC codes have better error performance than the corresponding LDPC block codes and random SC codes. The R&M construction of irregular SC QC LDPC codes is demonstrated. It is shown that low-complexity regular puncturing schemes can be deployed on these codes to construct families of rate-compatible irregular SC QC LDPC codes with good performance.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

We propose a novel concatenated coding scheme combined Low Density Parity Check(LDPC) code and vertical Bell Labs layered space-time (VBLAST) code to improve the bit error rate (BER) performance for Free-space optical (FSO) communication links with On Off Keying(OOK) modulation. In the scheme, π-rotation encoding and belief-propagation (BP) decoding algorithm are employed in LDPC code, and minimum mean-square error (MMSE) soft-decision decoding algorithm is used for VBLAST code. Moreover, a joint iterative detection and decoding algorithm of VBLAST code and LDPC code is used to improve the overall link performance. At last, the BER of the proposed scheme over lognormal atmospheric turbulent fading channels is analyzed by using Monte Carlo method. The result shows that the BER of the proposed concatenated coding scheme is much improved than that only use VBLAST code scheme.

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

RAID schemes have been in use for hard disk drives to provide improved performance or fault tolerance. RAID schemes, particularly RAID 2 and higher comprise of striping and adding parity. For solid state drives (SSDs), to combat die failures, schemes like RAID 5 and RAID 6 are effective. The idea is to have block level striping with distributed parity to provide data recovery in case of single or multiple die failures. In this work, we analyze the RAID 5 case used in SSDs when there is no die failure. For this case, the distributed parity information can be used to either combat higher raw bit error rate (RBER) or to improve the uncorrectable bit error rate (UBER). The algorithm we propose can be used with BCH or LDPC codes. With LDPC codes, it uses soft information on RAID 5 parity in order to recover from multiple error correcting code (ECC) fatals in a RAID stripe. The entire stripe data is read and then decoding is performed using the RAID parity to try recovery. We used simulations in order to characterize the RBER gains. First, modeling of the RBER distribution of the dies was performed using the log-normal distribution. Using this model, a performance evaluation for ECC schemes like LDPC codes and BCH codes was performed. We show that if LDPC codes are used, RAID 5 theoretically offers an RBER capability which is 3 times that of the error correcting code RBER capability. However, it is not possible to realize this RBER benefit completely since it has SSD performance downside. In order to meet the Quality of Service (QoS) specification, a realizable RBER gain is by a factor of 1.3 to 2 instead of 3. Further, these gains can only be realized if an LDPC code is used as an error correcting code, algebraic codes like BCH codes will provide limited gains. If no RBER benefit is permitted by a particular configuration of solid state drive, this scheme can be used to provide UBER gain by 3 orders of magnitude.