Evaluating security requirements in a general-purpose processor by combining assertion checkers with code coverage

Previous works have shown that high-level decision diagrams (HLDD-s) are suitable for system representation for analyzing code coverage metrics. This is due to the fact that HLDD models implicitly represent classical code coverage items, such as statement and branch coverage. However, research on the properties of HLDD-s, which contribute to the accuracy of coverage assessment, is missing. Current paper proposes a set of HLDD manipulations in order to generate diagrams that would allow more stringent code coverage measurement without sacrificing performance, i.e., computation time and memory requirements. The techniques include generation of HLDD-trees from Hardware Description Language (HDL)descriptions and two types of HLDD collapsing methods, which are a generalization of the BDD reduction rules. Experiments on ITC99 benchmark circuits show that the code coverage assessment based on the proposed HLDD manipulation is more stringent than what can be achieved with classical methods. At the same time, the model is well scalable because HLDD generation is terminated in the HDL variables.

Transistor density continues to increase exponentially, but power dissipation per transistor is improving only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the percentage of transistors that can switch at full frequency with each technology generation. Hence, while the transistor budget continues to increase exponentially, the power budget has become the dominant limiting factor in processor design. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve system performance.To trade transistors for energy efficiency in a scalable manner, we propose Quasi-specific Cores, or QsCores, specialized processors capable of executing multiple general-purpose computations while providing an order of magnitude more energy efficiency than a general-purpose processor. The QsCores design flow is based on the insight that similar code patterns exist within and across applications. Our approach exploits these similar code patterns to ensure that a small set of specialized cores support a large number of commonly used computations.We evaluate QsCores's ability to target both a single application library (e.g., data structures) as well as a diverse workload consisting of applications selected from different domains (e.g., SPECINT, EEMBC, and Vision). Our results show that QsCores can provide 18.4 x better energy efficiency than general-purpose processors while reducing the amount of specialized logic required to support the workload by up to 66%.

This session presents several experiences in the processor design domain for signal processing. The signal processing algorithms must generally support real hard real time constraints, and in this context the execution resources need to be very efficient. Designing specific processors or specific dedicated architectures is then a good issue to ensure the performances. Several specific architectures are presented in the following papers, and the authors present the result obtained and compare them with other solutions.

A new approach to application specific processor design is presented in this paper. Existing application specific processors are either based on existing general purpose processors or custom designed special purpose processors. The availability of a new technology, the Xilinx Logic Cell Array, presents the opportunity for a new alternative. The Flexible Processor Cell is a prototype of an extremely reconfigurable application specific processor. Flexible processors can potentially provide the performance advantages of special purpose processors as well as the cost advantages of general purpose processors. The flexible processor concept opens many potential areas for future research in processor architecture and implementation. This paper presents the design, implementation, and preliminary performance evaluation of an experimental flexible processor.

High performance reconfigurable computers (HPRCs), which combine general-purpose processors (GPPs) and field programmable gate arrays (FPGAs), are now commercially available. These interesting architectures allow for the creation of reconfigurable processors. HPRCs have already been used to accelerate integer and fixed-point applications. However, extensive parallelism and deeply pipelined floating-point cores are necessary to make MHz-scale FPGAs competitive with GHz-scale GPPs, thus making it difficult to accelerate certain kinds of floating-point kernels. Kernels with variable length nested loops, e.g., sparse matrix-vector multiply, have been problematic because of the loop-carried dependence associated with the pipelined floating-point units. While hardware description language (HDL)-based kernels have shown moderate success in addressing this problem, the use of a high-level language (HLL)-based approach to accelerate such applications has been rather elusive. If HPRCs are to become a part of mainstream military and scientific computing, we should emphasize the use of HLL-based programming, whenever possible, rather than HDL-based hardware design. The primary reason is the increased programmer productivity associated with HLLs when compared with HDLs. For example, the floating-point addition statement z = x+y, a single line in an HLL, corresponds to hundreds of lines of HDL. In this paper, we describe the design and implementation of a sparse matrix Jacobi processor to solve systems of linear equations, Ax=b. The parallelized, deeply pipelined, IEEE-754-compliant 32-bit floating-point sparse matrix Jacobi iterative solver runs on a contemporary HPRC. The FPGA-based components are implemented using only an HLL (the C programming language) and the Carte HLL-to-HDL compiler. An HLL-based streaming accumulator allows for the implementation of fully pipelined loops and results in a 2.5-fold wall clock runtime speedup when compared with an equivalent software-only implementation.

Today's software systems are too complex to ensure security after the fact – security has to be built into systems by design. To this end, model-based techniques such as UMLsec support the design-time specification and analysis of security requirements by providing custom model annotations and checks. Yet, a particularly challenging type of complexity arises from the variability of software product lines. Analyzing the security of all products separately is generally infeasible. In this work, we propose SecPL, a methodology for ensuring security in a software product line. SecPL allows developers to annotate the system design model with product-line variability and security requirements. To keep the exponentially large configuration space tractable during security checks, SecPL provides a family-based security analysis. In our experiments, this analysis outperforms the naive strategy of checking all products individually. Finally, we present the results of a user study that indicates the usability of our overall methodology.

This thesis work presents the implementation and validation of image processing problems in hardware to estimate the performance and precision gain. It compares the implementation for the addressed problem on a Field Programmable Gate Array (FPGA) with a software implementation for a General Purpose Processor (GPP) architecture. For both solutions the implementation costs for their development is an important aspect in the validation. The analysis of the flexibility and extendability that can be achieved by a modular implementation for the FPGA design was another major aspect. This work is based upon approaches from previous work, which included the detection of Binary Large OBjects (BLOBs) in static images and continuous video streams [13, 15]. One addressed problem of this work is the tracking of the detected BLOBs in continuous image material. This has been implemented for the FPGA platform and the GPP architecture. Both approaches have been compared with respect to performance and precision. This research project is motivated by the MI6 project of the Computer Vision research group, which is located at the Bonn-Rhein-Sieg University of Applied Sciences. The intent of the MI6 project is the tracking of a user in an immersive environment. The proposed solution is to attach a light emitting device to the user for tracking the created light dots on the projection surface of the immersive environment. Having the center points of those light dots would allow the estimation of the user’s position and orientation. One major issue that makes Computer Vision problems computationally expensive is the high amount of data that has to be processed in real-time. Therefore, one major target for the implementation was to get a processing speed of more than 30 frames per second. This would allow the system to realize feedback to the user in a response time which is faster than the human visual perception. One problem that comes with the idea of using a light emitting device to represent the user, is the precision error. Dependent on the resolution of the tracked projection surface of the immersive environment, a pixel might have a size in cm2. Having a precision error of only a few pixels, might lead to an offset in the estimated user’s position of several cm. In this research work the development and validation of a detection and tracking system for BLOBs on a Cyclone II FPGA from Altera has been realized. The system supports different input devices for the image acquisition and can perform detection and tracking for five to eight BLOBs. A further extension of the design has been evaluated and is possible with some constraints. Additional modules for compressing the image data based on run-length encoding and sub-pixel precision for the computed BLOB center-points have been designed. For the comparison of the FPGA approach for BLOB tracking a similar implementation in software using a multi-threaded approach has been realized. The system can transmit the detection or tracking results on two available communication interfaces, USB and RS232. The analysis of the hardware solution showed a similar precision for the BLOB detection and tracking as the software approach. One problem is the strong increase of the allocated resources when extending the system to process more BLOBs. With one of the applied target platforms, the DE2-70 board from Altera, the BLOB detection could be extended to process up to thirty BLOBs. The implementation of the tracking approach in hardware required much more effort than the software solution. The design of high level problems in hardware for this case are more expensive than the software implementation. The search and match steps in the tracking approach could be realized more efficiently and reliably in software. The additional pre-processing modules for sub-pixel precision and run-length-encoding helped to increase the system’s performance and precision.

Efficient and effective broadband wireless technologies are required to support the foreseeable need to process and exchange large amounts of data. In this Special Issue of the Springer Journal of Signal Processing Systems various disciplines of such efficiency and effectiveness in the context of Software-Defined Radio (SDR) technologies are discussed. At first, a selection of articles focuses on “spectral efficiency”. Since frequency spectrum is known to be scarce and limited, it becomes a resource of increasing value whose utilization must be handled with care. The rapidly growing demand for higher data throughputs in wireless communication does not allow inefficient use of spectrum anymore. Two promising approaches to tackle the “spectral efficiency” issue are Cognitive Radio (CR) and Dynamic Spectrum Access (DSA). A Cognitive Radio is capable of learning and adapting to its transmission environment. Taking e.g. spectrum sensing results into account, the decisions for accessing the scarce frequency spectrum in the most flexible and effective manner are made. CRs are typically based on SDR technology. Thus, the first set of articles puts emphasis on topics in the areas of Cognitive Radio, Cognitive Radio Networks, and Spectrum Sensing. The second selection of articles addresses the problems of “energy efficiency” and “implementation efficiency”. Especially in wireless communications these types of efficiencies are highly important to increase battery time of modern SDRbased platforms. The architectures of such SDRs are typically based on heterogeneous multi-processor hardware platforms hosting General Purpose Processors (GPP), Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) and sometimes even more specific processing elements. Each type of processor has a specific advantage in one or the other performance criterion like energy consumption, flexibility, processing time, throughput, waveform portability, components reusability etc. Whenever a new waveform shall be implemented on an SDR, the system designer has to take the decision for the best possible trade-off between all of these, partly conflicting, criteria under the given circumstances. For instance, the portability of waveform components can be improved by fulfilling the constraints of the Software Communications Architecture (SCA) specification and by using common Application Programming Interfaces (API). Thus, the second set of articles puts particular emphasis on topics in the areas of SDR and SCA Implementations.

Design of an ultra high speed AES processor for next generation IT security

In our research, we have proposed a reconfigurable architecture 'PARS' for general purpose. For developing software assets required as a general purpose processor, the PARS architecture introduces an I-PARS execution model as an ideal execution model for coarse-grained reconfigurable processors. The I-PARS execution model is based on an execution model of an extremely wide VLIW processor. With the use of the I-PARS execution model we are not only able to generate the configuration data for step by step execution mode as for the conventional processors, but also possible to generate configuration data for streaming execution mode, which works fine on reconfigurable processors. Further, as a processor supporting the above model efficiently, we designed a prototype PARS processor UNITE. We present the design of the UNITE processor, and show how we support the two execution modes on it. Also we introduce the compiler we are developing for the UNITE processor.

General-purpose many-core network processors have been widely used in network packet processing due to its high programmability and parallel processing ability.The design of general-purpose many-core network processors involves a lot of key technologies, including packet scheduling, inter-core communication, co-processing, etc.The verification of these technologies is essential before applied to the system.However, there are some of limitations in the current software-based verification platform, such as low simulation speed and fidelity.A FPGA-based verification platform for general-purpose manycore network processors (VeriNP) is proposed in this paper.The VeriNP supports verification of network processor for at least 16 real RISC CPU cores, and the frequent of cores can run at 100MHz or higher.Based on the VeriNP platform, two packet scheduling algorithms are studied and verified.

In software testing, code coverage can be one of the major metrics for evaluating the effectiveness of a test. Among all existing software testing methods, coverage-guided fuzzing is widely used nowadays, but the way it uses to obtain path coverage is mostly based on code instrumentation or emulation. However, a tester cannot take targeted measures if have no information about where the progress of the test is stuck. This paper proposes a method to record precise code coverage in a hybrid way which combining static program analysis and dynamic tracing. This work is on the basis of previous work that leverages hardware mechanism (Intel Processor Trace) to collect branch information and implement a tool called CovFuzz. Our approach can achieve an accurate coverage track that can reversibly find the corresponding source code or assembly code to assist program analysis and break through the bottleneck when the progress of software testing gets stuck. Our experiments show that the code coverage can be improved with the help of accurate path information.

In the age of computer evolution, the number of data grows swiftly. Moreover, the requirement of extracting the information from the database becomes urgent. Full-text search provides methods to quickly locate multiple keywords inside extensive text data and has gained more consideration in recent years. The proposed tools, such as Lucene, Hyper Estraier, and Namazu, are based on general-purpose processors. They spend more time on index input documents and require more space to store these indexes. In this work, we provide a text search processor design that could perform the full-text search without indexing. The text search processor offers a high-performance, high-level of parallelism and scalability. The design is deployed on Field Programmable Gate Arrays (FPGA) platforms. More than 70K processing units can be integrated on Xilinx Alveo U50. The working frequency achieves 266-MHz after place and route.

In this tutorial paper, we will outline a solution for prototyping, programming and implementing Application Specific Instruction-set Processors (ASIPs). A general introduction into this class of processor architectures and their characteristics is provided. The Synopsys Processor Designer tool suite and the LISA language for ASIP design are jointly introduced in the context of a H.264 design example. Finally, implementation results are presented.

Modern software systems evolve under tight delivery cycles, heterogeneous cloud deployments, and increasingly stringent security and compliance requirements. While machine learning (ML) has demonstrated promise for predicting defect-prone and vulnerability-prone components, many deployments remain bounded by data sparsity, limited execution context, and constrained throughput of dynamic testing. Meanwhile, high-performance computing (HPC) infrastructures provide abundant parallelism, yet they are often underutilized for software quality engineering workflows that require large-scale simulation, test amplification, and telemetry-driven analytics. This manuscript proposes an integrated ML + HPC methodology for accelerating defect and vulnerability discovery through high-throughput simulation analytics. The approach treats quality discovery as a throughput-optimized, data-centric pipeline: (i) generate execution diversity via scalable simulation and test amplification, (ii) capture and normalize multi-level telemetry from builds, tests, runtime traces, and security checks, (iii) learn ranking and classification models that prioritize code regions and change sets for deeper analysis, and (iv) close the loop with root-cause triage and remediation signals. We formalize the research gap as the missing coupling between predictive models and scalable execution diversity, and we outline an evaluation framework spanning prediction quality, defect and vulnerability yield, and end-to-end cost-per-finding. The resulting methodology enables software teams to scale discovery beyond conventional CI constraints, improving early warning capability and accelerating remediation in complex enterprise-grade systems.