Evaluation Method of Output Waveform Quality for Neutral-Point-Clamped Three-Level Converter

As the grid-connected AC-DC converter is the key equipment that links the low voltage direct current (LVDC) microgrids and the utility grid, the safe and stable operation of the converter is of great significance to improve the reliability of the LVDC microgirds. Since the converter's reliability is affected by the converter's topological structure and modulation strategy, a civil LVDC microgrid case study is analyzed, and the power losses, thermal stresses, lifetimes and reliability of components in the AC-DC converters with different topologies and modulation strategies are evaluated in this paper. The influence of these two factors on the reliability and efficiency of the converter is discussed, and the normalized weighted total harmonic distortion (NWTHD) with different modulation strategies is analytically determined and compared. The results show that when the converter operates with unity power factor in this application scenario, among the two-level converter, flying capacitor converter, neutral point clamped (NPC) converter and T-type converter, the T-type converter has the highest reliability. The effects of the converter's topology and modulation strategy on the capacitor reliability are relatively small. In view of reliability and power quality, third harmonic injection pulse width modulation (THIPWM) or space vector pulse width modulation (SVPWM) is more suitable for the converter in this microgrid.

ABSTRACTThis paper proposes a novel Space Vector Pulse Width Modulation strategy extending conventional 2-D SVPWM strategies for its use in three-phase four-leg inverters. The methodology is based on the segregation of the zero sequence from any initial desired unbalance voltage set-points. In this way, the operation of the fourth leg is reserved to manage the desired homopolar component and to compensate for the inherent homopolar component provided by any 2-D SVPWM technique. This choice not only minimizes the complexity and effort to determine the location of the reference voltage space vector from a 3-D to a 2-D space but also enables to use 75% of the affordable space to synthesize voltages under a 3-D SVPWM technique. Furthermore, the proposal is compared with other four 3-D SVPWM techniques analysing the advantages in terms of execution time, memory program, simplicity and neutral to mid-point voltage quality, resulting into a really good implementing alternative compared with the major 3-D SPVWM techniques analysed. The new modulation strategy is presented in detail, and a complete set of simulations using this particular modulation strategy has been done, and the results of these simulations have been validated on a laboratory set-up using a four-leg inverter.

Multilevel inverters are increasingly being used in high-power medium voltage applications due to their superior performance compared to two-level inverters. Among various modulation techniques for a multi-level inverter, the space vector pulse width modulation (SVPWM) is widely used. The complexity is due to the difficulty in determining the location of the reference vector, the calculation of on times, and the determination and selection of switching states.This paper proposes a general SVPWM algorithm for Multi-level inverters based on standard two-level SVPWM . To control multilevel converters, the pulse width modulation (PWM) strategies are the most effective, especially the space vector pulse width modulation (SVPWM) one, which has equally divided zero voltage vectors describing a lower total harmonic distortion (THD). In this work, a three and four-level inverter using space vector modulation strategy has been modeled and simulated with a passive R-L load. Simulation results are presented for various operation conditions to verify the system model.

A fast algorithm for three-level space vector pulse wide modulation (SVPWM) in neutral point clamped (NPC) inverters based on traditional three-level sinusoidal pulse wide modulation (SPWM) is proposed. The acting time relation of each state in each phase is got by deeply researching the similarities and differences of three-level SPWM and SVPWM. This algorithm can realize all kinds of state sequences easily, it does not need to do trigonometric function, irrational operation and coordinate transformation, it just needs ordinary arithmetic, therefore the calculation is very simple and the result is much more accurate. The fast algorithm can be easily implemented on microprocessor and the executing speed is faster than the conventional three-level SVPWM algorithm.

A simple real time space vector pulse width modulation (PWM) strategy for high-performance converters is presented. The application of the proposed modulator in AC-to-AC rectifier and DC-to-DC inverter systems is investigated. In AC-to-DC rectifier systems the proposed modulator adapts to any voltage unbalance or distortion in the input and suitably generates gating signals to maintain high-quality output voltage. In DC-to-AC inverter systems the proposed system maintains a low THD at the output terminals even with substantial voltage ripple in the input DC. Implementation of the proposed system on a TMS 320 C30 DSP (digital signal processor) is suggested, and selected results are experimentally verified.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The aim of this paper is to obtain the AC voltage from DC source with the help of Space vector based Inverter. In a space-vector PWM (Pulse Width Modulation) inverter, which is widely used, the voltage utilization factor can be increased to 0.906, normalized to that of the six step operation. Three phase voltage-source pulse width modulation inverters have been widely used for dc/ac power conversion since they can produce a variable voltage and variable frequency power. However, they require a dead time to avoid the arm-short and snubber circuits to suppress the switching spike. Apart from these ancillary aspects, the PWM inverters have an essential problem that they cannot produce voltages as large as the six-step inverters can. That is, the dc bus voltage cannot be utilized to the maximum. To increase the voltage utilization of the sinusoidal PWM inverter, a method of the addition of the third harmonics to the reference voltage was proposed by which the fundamental component can be increased by 15.5%. In a space-vector PWM inverter, which is widely used, the voltage utilization factor can be increased to 0.906, normalized to that of the sixstep operation. On the other hand, different discontinuous PWM strategies were analyzed, where the modulation waveform of a phase has at least one segment of 60 which is clamped to the positive and/or negative dc bus for, at most, a total of 120 in a fundamental period during which no switching in either inverter arm occurs. Recently, it is shown that discontinuous PWM schemes and the space-vector PWM can be obtained by properly adding a zero-sequence voltage to the original modulation waveform.

The use of wireless charging technology for Electric Vehicles (EVs) is gaining increasing significance due to its ability to charge batteries safely and conveniently without the need for physical connectors. This paper presents the design and implementation of the transmitter-side power conversion system for a wireless EV charging station. The proposed system architecture integrates a front-end Power Factor Correction (PFC) rectifier, an Interleaved Resonant DC-DC converter, and a three-level Neutral Point Clamped (NPC) inverter, providing a highly efficient and stable power transmission path for battery charging. The Interleaved Resonant DC-DC converter, designed with a Zero Voltage Switching (ZVS) mechanism, minimizes switching losses and enhances overall efficiency. Its operation under Constant Current (CC) and Constant Voltage (CV) control modes ensures smooth and reliable mode transition through an auxiliary controller incorporated alongside a conventional PI controller. The inverter stage adopts a Modified Space Vector Pulse Width Modulation (MSVPWM) strategy that significantly reduces Total Harmonic Distortion (THD) in both voltage and current waveforms, thereby maintaining compliance with power quality standards. The complete system's performance has been evaluated through both simulation and experimental validation. MATLAB/Simulink-based analysis demonstrates stable converter dynamics with a regulated output voltage of 325 V and negligible transient disturbances during mode transitions. A 0.2 kW laboratory prototype was developed to confirm the simulation results using PIC24F16KA102 and FPGA-SPARTAN-7 controllers for power and switching signal generation, respectively. Experimental measurements indicate that the proposed Interleaved Resonant DC-DC converter achieved an efficiency of approximately 95.35% at rated load, which aligns closely with theoretical predictions. The three-level NPC inverter produced a 320 V output with voltage and current THD levels of 4.8% and 5.6%, respectively. A 2:1 air-core transformer designed for high-frequency operation (100-200 kHz) effectively transfers power to the EV receiver side. The influence of coupling coefficient and air-gap variation on transfer efficiency was systematically investigated, revealing an optimal separation distance of 10-20 mm. The overall results confirm the efficacy of the proposed design for high-efficiency wireless EV charging. Future work will concentrate on optimizing the receiver-side converters to further enhance system efficiency and dynamic performance.

Dual three-phase permanent-magnet synchronous machines (DTP-PMSM) connected with a single neutral point provide a loop for zero-sequence current (ZSC). This paper proposes a novel space vector pulse width modulation (SVPWM) strategy to suppress the ZSC. Five vectors are selected as basic voltage vectors in one switching period. The fundamental and harmonic planes and the zero-sequence plane are taken into consideration to synthesis the reference voltage vector. To suppress the ZSC, a non-zero zero-sequence voltage (ZSV) is generated to compensate the third harmonic back-EMF. Rather than triangular carrier modulation, the sawtooth carrier modulation strategy is used to generate asymmetric PWM signals. The modulation range is investigated to explore the variation of modulation range caused by considering the zero-sequence plane. With the proposed method, the ZSC can be considerably reduced. The simulated and experimental results are presented to validate the effectiveness of the proposed modulation strategy.

The Variable Frequency Drives (VFD) are a common type of controlling the speed of 3-phase induction motors which are based on two control modulation techniques of Voltage Source Inverter: Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SV-PWM). The SPWM control technique is known as an easier implementation, but the SV-PWM control technique can be distinguished by an easier digital realization and a better utilization of DC bus. All 3-phase PWM inverters produce a total harmonic distortion (THD) on its output, which causes electromechanical and thermal stresses. The aim of this paper is comparing the low order current harmonics while driving an unbalanced 3-phase induction motor (the case of deterioration of the insulation as a result of inter-turn short circuits between few turns of the same phase) using SPWM and SV-PWM two-level 3-phase Voltage Source Inverters (VSI). For this type of unbalanced 3-phase induction motor, the SVPWM and SV-PWM schemes are modeled and simulated using Matlab/Simulink software. A detailed comparative analysis of THD-phase currents is made for both modulation strategies at different switching frequencies while keeping the constant amplitude modulation index.

Multilevel inverters are increasingly being used in high-power medium voltage industrial drive applications due to their superior performance compared to conventional two-level inverters. Thre are a number of Pulse width modulation (PWM) techniques applied in recent years. The most widely applied PWM techniques are Sine Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM). SPWM is the most simple modulation technique that can realize easily in analog circuit. However, it has some drawbacks such as higher total harmonic distortion (THD), lower effective DC utilization and lower switching frequency. Space vector pulse width modulation (SVPWM) is widely used because of their easier digital realization and better DC bus utilization and lower THD. The complexity is due to the difficulty in determining the reference vector location, on times calculation, and switching states selection. This paper presents a simple SVPWM algorithm for diode clamped three level inverters based on standard two-level SVPWM which can easily determine the location of reference vector, calculate the on-times, the selection of switching states. Three level diode clamped inverter (3LDCI) using space vector modulation technique has been modeled and simulated using MATLAB/SIMULINK and Origin 6.1 with a passive R-L load that can be extended to any level. Simulation results are presented to verify the proposed SVPWM control in terms of THD. The results are compared with conventional sinusoidal pulse width modulation (SPWM) where SVPWM shows better performance than SPWM in terms of THD. DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.6038

Purpose This paper aims to present a modified space vector pulse width modulation (SVPWM) technique for six-phase induction motor drive based on common-mode voltage (CMV) and current losses which are two important issues affecting drive system behavior and quality. Design/methodology/approach It is shown that the presence of z-component currents and the presence of CMV in six-phase drive system are two major limiting factors in space vector selection. The behavior of several space vector selections in a two-level inverter considering minimum CMV and z-components is investigated. Then, the space vectors in a three-level inverter is analyzed and tried to explore an SVM technique with better behavior. Findings The analyses show that all the problems cannot be solved in a six-phase drive system with two-level inverter despite having 64 space vectors; this study tried to overcome the limitations by exploring space vectors in a three-level inverter. Originality/value The proposed pulse width modulation (PWM) strategy leads to minimum current distortion and undesired current components with zero CMV and modest torque ripple.

Pulse width modulation (PWM) strategies for the control of asymmetrical six-phase drives have been widely studied since the beginning of this century. Carrier-based and different space vector PWM algorithms have been developed and evaluated. Nevertheless, there are still some challenges that require research work in this field. This paper deals with this topic, and introduces three space vector techniques. The methods are based in a recently developed scheme that combines the nearest two medium and two large size voltage vectors to synthesise the reference vector. The schemes enable either sinusoidal or multifrequency output voltage operation modes. Theoretical derivation supported by closed-loop tests demonstrate the viability and potential of the proposal.

In this paper, a new hybrid multilevel six-phase machine drive system topology is proposed and investigated. Such topology is composed of two three-level three-phase neutral-point-clamped (NPC) inverters and a traditional two-level three-phase voltage source inverter (VSI) with isolated DC-links feeding the open-end windings (OEW) of a six-phase induction motor (SPIM). The system model, operating principles, investigation of the common-mode voltage (CMV) generated and two space vector pulse width modulation (SV-PWM) strategies are presented. The first SV-PWM technique is based on three similar individual plans and its implementation by means of equivalent level-shifted PWM (LS-PWM). The second technique is based on multidimensional approach. Both techniques used are able to generate multilevel voltage waveforms with reduced switching stress, which is suitable for high power applications with voltage and current restrictions. The performance of the system is compared with a standard configuration. It has demonstrated some advantages such as: (i) reduced number of isolated DC-link capacitor banks, (ii) lower harmonic distortion of the machine currents, (iii) possibility to use three different ratios of DC-link voltage. The feasibilty of the system is demonstrated by simulation and experimental results.

This paper is to present a new space vector pulse width modulation (PWM) algorithm for four switch three phase inverter (FSTPI) fed induction motor under DC-link voltage imbalance. By using reasonable mathematical transform, space vector PWM (SVPWM) technique for FSTPI under DC-link voltage imbalance or ripples have been solved, which is based on the establishment of basic space vectors and modulation technique in similarity with six-switch three-phase inverters. This approach has a very important sense to solve hard problems for FSTPI under DC-link voltage imbalance, for example ensuring the required voltage for undermodulation mode and overmodulation mode 1 and 2, extended to six-step mode. Matlab/Simulink is used for the simulation of the proposed SVPWM algorithm for undermodulation, overmodulation mode 1 and 2. This SVPWM approach is also validated experimentally using DSP TMS320LF2407a in FSTPI-IM system.

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent dual three-phase SVPWM realization are proposed in this paper, which is suitable for two-level six-phase voltage inverter fed asymmetrical dual stator induction machines (DSIMs). The DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees. The proposed SVPWM technique can reduce the torque ripple and suppress the harmonic currents flowing in stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the dual three-phase SVPWM technique has been demonstrated, which allows easy implementation for digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.