Evolutionary Algorithms in the Classification of Mammograms

Evolutionary algorithms (EAs) are population-based search algorithms that have been successfully applied to solve hard optimization problems in many application domains. Since the early 1990's researchers have begun to apply evolutionary algorithms to synthesize electronic circuits. Nowadays it is evident that the evolutionary design approach can automatically create efficient electronic circuits in many domains. In this tutorial, fundamental concepts of evolutionary design of digital circuits are presented. In particular, the tutorial deals with Cartesian Genetic Programming (CGP) — a method of genetic programming that in many cases outperforms conventional synthesis tools in terms of achievable circuit size reduction. Innovative designs will be presented in domains of small combinational circuits (where the goal is to minimize the number of gates), middle-size circuits (such as image filters intended for FPGAs where the goal is to obtain the quality of filtering of conventional methods for a significantly lower cost on a chip) and large circuits (such as benchmark circuits for comparison of testability analysis methods), covering thus circuit complexity from a few gates to millions of gates. For example, one of evolved image filters is now protected by utility model in the Czech Republic (patent pending). Evolved circuits will be compared with the best-known conventional designs. We will also show how to deal with the so-called scalability problems of evolutionary design which have been identified as the most important problems from the point of view of practical applications. In summary, tutorial participants will become familiar with the state of the art methods in the area of digital circuit evolution. They will learn how to apply CGP, construct the fitness function and run experiments.

Evolutionary design for energy-efficient approximate digital circuits

Graph representations promise several desirable properties for genetic programming (GP); multiple-output programs, natural representations of code reuse and, in many cases, an innate mechanism for neutral drift. Each graph GP technique provides a program representation, genetic operators and overarching evolutionary algorithm. This makes it difficult to identify the individual causes of empirical differences, both between these methods and in comparison to traditional GP. In this work, we empirically study the behaviour of Cartesian genetic programming (CGP), linear genetic programming (LGP), evolving graphs by graph programming and traditional GP. By fixing some aspects of the configurations, we study the performance of each graph GP method and GP in combination with three different EAs: generational, steady-state and (1+lambda ). In general, we find that the best choice of representation, genetic operator and evolutionary algorithm depends on the problem domain. Further, we find that graph GP methods can increase search performance on complex real-world regression problems and, particularly in combination with the (1 + lambda) EA, are significantly better on digital circuit synthesis tasks. We further show that the reuse of intermediate results by tuning LGP’s number of registers and CGP’s levels back parameter is of utmost importance and contributes significantly to better convergence of an optimization algorithm when solving complex problems that benefit from code reuse.

This chapter describes the use of biologically inspired Evolutionary Algorithms (EAs) to create designs for implementation on a reconfigurable logic device. Previous work on Evolvable Hardware (EHW) is discussed with a focus on timing problems for digital circuits. An EA is developed that describes the circuit using a Hardware Description Language (HDL) in a Cartesian Genetic Programming (CGP) framework. The use of an HDL enabled a commercial hardware simulator to be used to evaluate the evolved circuits. Timing models are included in the simulation allowing sequential circuits to be created and assessed. The aim of the work is to develop an EA that is able to create time dependent circuity using the versatility of a HDL and a hardware timing simulator. The variation in the circuit timing from the placement of the logic components, led to an environment with a selection pressure that promoted a more robust design. The results show the creation of both combinatorial and sequential circuits.

Dispatching rules are most commonly used to solve scheduling problems under dynamic conditions. Since designing new dispatching rules is a time-consuming process, it can be automated by using various machine learning and evolutionary computation methods. In previous research, genetic programming has been the most commonly used method for automatically designing new dispatching rules. However, there are many other evolutionary methods that use representations other than genetic programming that can be used to create dispatching rules. Some, such as gene expression programming, have already been used successfully, while others, such as Cartesian genetic programming or grammatical evolution, have not yet been used to generate dispatching rules. In this paper, six different methods (genetic programming, gene expression programming, Cartesian genetic programming, grammatical evolution, stack representation, and analytic programming) for generating dispatching rules for the unrelated machines environment are tested and the results for various scheduling criteria are analysed. It is also analysed how different individual sizes in the tested methods affect the performance and average size of the generated dispatching rules. The results show that, with the exception of grammatical evolution and analytic programming, all tested methods perform quite similarly, with results depending on the selected scheduling criterion. The results also show that Cartesian genetic programming is the most resistant to the occurrence of bloat and evolves dispatching rules with the smallest average size.

Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.

On the feasibility of using evolvable hardware for hardware Trojan detection and prevention

Approximate computing along with quantized low-precision computing has gained significant interest in today’s neural network (NN) implementation. This paper proposes a library of VLSI implementations of different activation functions, aimed towards designing hardware-efficient NN accelerators. Cartesian genetic programming (CGP), an evolutionary algorithm was employed to generate gate-level designs of approximate and exact representations of activation functions. We open-source the hardware library of 9444 circuits containing a majority of the activation functions employed in NN architectures, including Sigmoid, Hyperbolic-Tangent, Gaussian, ReLU, GeLU, Softplus, and Binary-Step. The library also presents the error characteristics and hardware metrics of the designs which will aid in the usage of the library in future research. Additionally a hardware comparison of the proposed circuits against existing implementations including piecewise-linear (PWL), memory-based, hls4ml, DNNweaver implementations to realize activation functions on FPGA and ASIC flow is presented. The CGP evolved hardware library shows minimal silicon space requirement, least power consumption when investigated for ASIC flow, and the least LUT utilization’s in FPGA flow. Besides, SOMALib designs are purely combinatorial, allowing various synthesis stage optimizations towards the target Power-Performance-Area budget, which is not possible in standard memory block implementations.

For the evolutionary algorithm, the representation of the electronic circuit has two methods, one kind is code with the electronic circuit solution space, the other is code with the problem space. How one representation quality weighs may think the following questions? The first is the code method should as far as possible complete, it is say for the significance solution circuit or the optimize solution obtains in the problem space may represented by this code method. The second is the code method should speeds up the convergence speed of the algorithm search. The hardware representation methods mainly include binary bit string representation, tree representation, Cartesian Genetic Programming representation and other representations. In this paper, we introduce the representations of the binary bit string and Cartesian Genetic Programming in detail, and based on the two representations we design the evolutionary algorithm for electronic circuits optimization. Then we introduce the encoding of the circuit as a chromosome, the genetic operators and the fitness function of our algorithm. For the case studies showed this algorithm has proved to be efficient, and the experiment results showed that we have gained better results.

Lately, evolutionary algorithms have gained traction due to their ability to produce state-of-the-art deep learning architectures for a given data set, even though they require considerable amount of compute resources, they are a heavily researched domain because of the complexities involved in designing deep learning architectures. Currently, none of the evolutionary approaches available have incorporated the attention mechanism, which is a proven technique to improve the performance of image classification and language models. This paper posits a neuroevolutionary technique coupled with the use of Convolution Block Attention Module for image classification. As technology progresses, it’s inevitable that there will be massive advancements leading to cheaper and more available computing making evolutionary approaches a promising avenue to develop task specific deep learning models. The proposed approach evolves a topology that achieves a high fitness of 87.44%, using fewer parameters as compared to previous approaches. This results in a superior fitness score compared to most past approaches, despite being evolved for just few generations.

Multi-sensor fusion: an Evolutionary algorithm approach

A specific algorithm is presented for the automatic extraction of breast tumors. This algorithm involves 3D adaptive K-means clustering of the gray-scale and texture features images. The segmentation problem is formulated as a Maximum A Posterior (MAP) estimation problem. The MAP estimation is achieved using Besag's Iterated Conditional Modes algorithm for the minimization of an energy function. This function has three components. The first one constrains the region to be close to the data, the second imposes spatial continuity and the third takes into consideration the texture of the various regions. This segmentation technique is demonstrated on in vivo breast data. The method revealed very efficient. The results are compared with the manual segmentation of lesions by an expert.

This study presents a computer aided system for automatic detection and classification of breast cancer in mammogram images. First the suspicious region or the Region of Interest is identified and extracted using Intuitionistic Fuzzy C-Means Clustering technique. Next multilevel Discrete Wavelet Transformation is applied to the extracted Region of Interest. After applying Discrete Wavelet Transformation, histogram features, Gray Level Concurrence wavelet features, and wavelet energy features are extracted from each Region of Interest of the image. Before classification, Principal Component Analysis is applied on the extracted features to reduce the feature dimension. Finally, the feature database is submitted to self-adaptive resource allocation network classifier for classification. The proposed system is verified with 295 mammograms in the Mammographic Image Analysis Society Database. The result shows that the proposed algorithm produces better results.

Constrained optimization is a computationally difficult task, particularly if the constraint functions are nonlinear and non-convex. As a generic classical approach, the penalty function approach is a popular methodology which degrades the objective function value by adding a penalty proportional to the constraint violation. However, the penalty function approach has been criticized for its sensitivity to the associated penalty parameters. Since its inception, evolutionary algorithms have been modified in various ways to solve constrained optimization problems. Of them, the recent use of a bi-objective evolutionary algorithm in which the minimization of the constraint violation is included as an additional objective has received significant attention. In this article, a combination of a bi-objective evolutionary approach with the classical penalty function methodology is proposed, in a manner complementary to each other. The evolutionary approach provides an appropriate estimate of the penalty parameter, while the solution of an unconstrained penalized function by a classical method induces a convergence property to the overall hybrid algorithm. The working of the procedure on a number of standard numerical test problems and an engineering design problem is demonstrated. In most cases, the proposed hybrid methodology is observed to take one or more orders of magnitude fewer function evaluations to find the constrained minimum solution accurately than some of the best reported existing methodologies.

The paper presents the development of a computer-aided diagnostic (CAD) system for the early detection of endometrial cancer. The proposed CAD system supports reproducibility through texture feature standardization, standardized multifeature selection, and provides physicians with comparative distributions of the extracted texture features. The CAD system was validated using 516 regions of interest (ROIs) extracted from 52 subjects. The ROIs were equally distributed among normal and abnormal cases. To support reproducibility, the RGB images were first gamma corrected and then converted into HSV and YCrCb. From each channel of the gamma-corrected YCrCb, HSV, and RGB color systems, we extracted the following texture features: 1) statistical features (SFs), 2) spatial gray-level dependence matrices (SGLDM), and 3) gray-level difference statistics (GLDS). The texture features were then used as inputs with support vector machines (SVMs) and the probabilistic neural network (PNN) classifiers. After accounting for multiple comparisons, texture features extracted from abnormal ROIs were found to be significantly different than texture features extracted from normal ROIs. Compared to texture features extracted from normal ROIs, abnormal ROIs were characterized by lower image intensity, while variance, entropy, and contrast gave higher values. In terms of ROI classification, the best results were achieved by using SF and GLDS features with an SVM classifier. For this combination, the proposed CAD system achieved an 81% correct classification rate.