Experience with active messages on the Meiko CS-2

Computation-intensive tensor operators constitute over 90% of the computations in Large Language Models (LLMs) and Deep Neural Networks. Automatically and efficiently generating high-performance tensor operators with hardware primitives is crucial for diverse and ever-evolving hardware architectures like RISC-V, ARM, and GPUs, as manually optimized implementation takes at least months and lacks portability. LLMs excel at generating high-level language codes, but they struggle to fully comprehend hardware characteristics and produce high-performance tensor operators. We introduce a tensor-operator auto-generation framework with a one-line user prompt (QiMeng-TensorOp), which enables LLMs to automatically exploit hardware characteristics to generate tensor operators with hardware primitives, and tune parameters for optimal performance across diverse hardware. Experimental results on various hardware platforms, SOTA LLMs, and typical tensor operators demonstrate that QiMeng-TensorOp effectively unleashes the computing capability of various hardware platforms, and automatically generates tensor operators of superior performance. Compared with vanilla LLMs, QiMeng-TensorOp achieves up to 1291× performance improvement. Even compared with human experts, QiMeng-TensorOp could reach 251% of OpenBLAS on RISC-V CPUs, and 124% of cuBLAS on NVIDIA GPUs. Additionally, QiMeng-TensorOp also significantly reduces development costs by 200× compared with human experts.

Mobile agents are a competitive concept of client-server computing and are especially suitable in mobile environments, that are characterized by low bandwidth communication facilities and ad hoc connection/disconnection to stationary systems. They can be used for information retrieval and information filtering, in which case they evaluate replies and return only the relevant data. Mobile agents as a metaphor of active objects are created on a mobile device such as a Personal Digital Assistant (PDA), will be launched into the information galaxy and are fulfilling the mobile user ‘s task on the services available on networked stationary systems. One transmission channel for these itinerant agents is email. This paper introduces Active M 3 as an example of an active mail framework, which can be regarded as a first approach in authoring mobile agents in a graphical interactive manner. Active M 3 integrates two known concepts: active mail and multimedia mail.The idea of active or computational mail has existed since 1976 (3); transfer programs embedded in standard mail which automatically execute at the receivers site. This hiker —the active mail message— can also carry multimedia elements (audio, animation, image etc, and indeed sub-agents) in his backpack, which it can also render and orchestrate at the receivers site in a sophisticated manner. Therefore, synchronization concepts are introduced. To summarize, the objective of Active M 3 is the development and implementation of a system for the realization of active multimedia mail and a composing tool as an easy to use interactive authoring environment. An extension towards a more generalized authoring environment for this remote programming concept enables authoring of mobile agents.This paper introduces the basic ideas. The results of the proposed concept for a composer for active multimedia mail are presented through a realized prototype.KeywordsActive MailComputational MailMultimedia MailMIMERemote ProgrammingMo-bile AgentsItinerant AgentsSynchronization

AbstractÐIn the past decade, the exponential growth in commodity CPU's speed has far outpaced advances in memory latency. A second trend is that CPU performance advances are not only brought by increased clock rate, but also by increasing parallelism inside the CPU. Current database systems have not yet adapted to these trends and show poor utilization of both CPU and memory resources on current hardware. In this paper, we show how these resources can be optimized for large joins and translate these insights into guidelines for future database architectures, encompassing data structures, algorithms, cost modeling, and implementation. In particular, we discuss how vertically fragmented data structures optimize cache performance on sequential data access. On the algorithmic side, we refine the partitioned hash-join with a new partitioning algorithm called radix-cluster, which is specifically designed to optimize memory access. The performance of this algorithm is quantified using a detailed analytical model that incorporates memory access costs in terms of a limited number of parameters, such as cache sizes and miss penalties. We also present a calibration tool that extracts such parameters automatically from any computer hardware. The accuracy of our models is proven by exhaustive experiments conducted with the Monet database system on three different hardware platforms. Finally, we investigate the effect of implementation techniques that optimize CPU resource usage. Our experiments show that large joins can be accelerated almost an order of magnitude on modern RISC hardware when both memory and CPU resources are optimized. Index TermsÐMain-memory databases, query processing, memory access optimization, decomposed storage model, join algorithms, implementation techniques. 1

Mobile context-aware applications have specific needs regarding data communications and position sensing, that current standard hardware is still not able to fulfill. Current mechanisms are inadequate for applications that need constant communications because of their high power needs and low precision when used to measure the physical indoor position of a mobile device. For this reason the authors have created a new, flexible and inexpensive technology that aims to solve both the needs of communication and position estimation on mobile platforms. This new network type uses recently developed technology to minimize power consumption, leading to a longer battery life and maximizing the precision of the position sensing of the device. Finally, on top of their hardware platform they have devised a software layer, named Kindergarten, which allows high-level languages to interact with the underlying hardware.

With the fast development of embedded Web, the needs of communication between different embedded devices through Internet become increasingly intense. Taking application requirements into account, we utilized a customized embedded 32-bit processsor as the hardware platform which contains a MAC module. On this basis. We design the protocol layer network interface and a network driver based on descriptor-based DMA transfer mechanism. In the design of the data storage on NIC, we use a descriptor linked list and a data buffer to achieve sending data and receiving data between MAC and CPU. In the design, chain descriptor is used in both sending and receiving procedures. In addition, while receiving or sending data to PHY, we use the superset MII instead of RMII for as easier expression.

Control of large distributed cloud-based services is a challenging problem. The Distributed Rate Limiting (DRL) paradigm was recently proposed as a mechanism for tackling this problem. The heuristic nature of existing DRL solutions makes their behavior unpredictable and analytically untractable. In this paper we treat the DRL problem in a mathematical framework and propose two novel DRL algorithms that exhibit good and predictable performance. The first algorithm Cloud Control with Constant Probabilities (C3P) solves the DRL problem in best effort environments, emulating the behavior of a single best-effort queue in a fully distributed manner. The second problem we approach is the DRL in processor sharing environments. Our algorithm, Distributed Deficit Round Robin (D2R2), parameterized by parameter α, converges to a state that is, at most, O(1/α) away from the exact emulation of centralized processor sharing queue. The convergence and stability properties are fully analyzed for both C3P and D2R2. Analytical results are validated empirically through a number of representative packet level simulations. The closed-form nature of our results allows simple design rules which, together with extremely low communication overhead, makes the presented algorithms practical and easy to deploy.

Latency hiding techniques such as multilevel cache hierarchies yield high performance when applications map well onto hierarchy implementations, but performance can suffer drastically when they do not. Identifying and reducing mismatches between an application and the memory hierarchy is difficult without insight into the actual behavior of the hardware implementation. We advocate the use of hardware event counters, as a cheap, effective and practical way to tune applications for a given hardware platform. We take a case study approach, focussing on the counters available on the SPARCcenter 2000, a 20 processor, shared-bus based multiprocessor. We describe the tools we built to relate hardware event counts to user applications and give examples to illustrate how these tools are useful in practice. We conclude with a critique of the current hardware counters, offering a user's perspective on how they could be redesigned to be more effective.

Sorting is an important component of many applications, and parallel sorting algorithms have been studied extensively in the last three decades. One of the earliest parallel sorting algorithms is bitonic sort, which is represented by a sorting network consisting of multiple butterfly stages. The paper studies bitonic sort on modern parallel machines which are relatively coarse grained and consist of only a modest number of nodes, thus requiring the mapping of many data elements to each processor. Under such a setting optimizing the bitonic sort algorithm becomes a question of mapping the data elements to processing nodes (data layout) such that communication is minimized. The authors developed a bitonic sort algorithm which minimizes the number of communication steps and optimizes the local computation. The resulting algorithm is faster than previous implementations, as experimental results collected on a 64 node Meiko CS-2 show.

The recent progress in Machine Learning (Géron, 2022) and particularly Deep Learning (Goodfellow, 2016) models exposed the limitations of traditional computer architectures. Modern algorithms demonstrate highly increased computational demands and data requirements that most existing architectures cannot handle efficiently. These demands result in training speed, inference latency, and power consumption bottlenecks, which is why advanced methods of computer architecture optimization are required to enable the development of ML/DL-dedicated efficient hardware platforms (Engineers, 2019). The optimization of computer architecture for applications of ML/DL becomes critical, due to the tremendous demand for efficient execution of complex computations by Neural Networks (Goodfellow, 2016). This paper reviewed the numerous approaches and methods utilized to optimize computer architecture for ML/DL workloads. The following sections contain substantial discussion concerning the hardware-level optimizations, enhancements of traditional software frameworks and their unique versions, and innovative explorations of architectures. In particular, we discussed hardware including specialized accelerators, which can improve the performance and efficiency of a computation system using various techniques, specifically describing accelerators like CPUs (multicore) (Hennessy, 2017), GPUs (Hwu, 2015) and TPUs (Contributors, 2017), parallelism in multicore architectures, data movement in hardware systems, especially techniques such as caching and sparsity, compression, and quantization, other special techniques and configurations, such as using specialized data formats, and measurement sparsity. Moreover, this paper provided a comprehensive analysis of current trends in software frameworks, Data Movement optimization strategies (A.Bienz, 2021), sparsity, quantization and compression methods, using ML for architecture exploration, and, DVFS (Hennessy, 2017),, which provides strategies for maximizing hardware utilization and power consumption during training, machine learning, dynamic voltage, and frequency scaling, runtime systems. Finally, the paper discussed research opportunity directions and the possibilities of computer architecture optimization influence in various industrial and academic areas of ML/DL technologies. The objective of implementing these optimization techniques is to largely minimize the current gap between the computational needs of ML/DL algorithms and the current hardware’s capability. This will lead to significant improvements in training times, enable real-time inference for various applications, and ultimately unlock the full potential of cutting-edge machine learning algorithms.

OpenAirInterface is an experimental open-source real-time hardware and software platform for experimentation in wireless communications and signal processing. With the help of OpenAirInterface, researchers can demonstrate novel ideas quickly and verify them in a realistic environment. Its current implementation provides a full open-source software modem comprising physical and link layer functionalities for cellular and mesh network topologies. The physical (PHY) layer of the platform targets fourth generation wireless networks and thus uses orthogonal frequency division multiple access (OFDMA) together with multiple-input multiple-output (MIMO) techniques. The current hardware supports 5 MHz bandwidth and two transmit/receive antennas. The media access (MAC) layer of the platform supports an abundant two-way signaling for enabling collaboration, scheduling protocols, as well as traffic and channel measurements. In this paper, we focus on the mesh topology and show how to implement a single-frequency mesh network with OpenAirInterface. The key ingredients to enable such a network are a dual-stream MIMO receiver structure and a distributed network synchronization algorithm. We show how to implement these two algorithms in real-time on the OpenAirInterface platform. Further more, we provide results from field trials and compare them to the simulation results.

HD video data is visible in the real-time compression processing is one of the key technologies, The current video compression codec hardware platform mainly includes: ASIC, DSP and SoC. These three kinds of SOC chips have become the mainstream of the codec chip market because of their low cost, low power consumption and high integration. According to Da Vinci of TI processor TMS320DM368 as the core architecture, The hardware system of high definition video compression processing based on embedded technology is designed, which includes video input ISIF interface module, communication module, core processor module, peripheral circuit module and power module. This system supports 1080P30 HD video capture hardware frame, H.264 encoding compression and local storage, can be widely used in industrial control, medical, aerospace and other industries, has important application value in engineering.

Virtualization has been purported to be a panacea for many security problems. We analyze the feasibility of constructing an integrity-protected hypervisor on contemporary x86 hardware that includes virtualization support, observing that without the fundamental property of hypervisor integrity, no secrecy properties can be achieved. Unfortunately, we find that significant issues remain for constructing an integrity-protected hypervisor on such hardware. Based on our analysis, we describe a set of necessary rules that must be followed by hypervisor developers and users to maintain hypervisor integrity. No current hypervisor we are aware of adheres to all the rules. No current x86 hardware platform we are aware of even allows for the construction of an integrity-protected hypervisor. We provide a perspective on secure virtualization and outline a research agenda for achieving truly secure hypervisors.

High-density orchard systems have become increasingly prevalent in modern fruit production due to their potential for maximizing yield per unit area, yet they present significant challenges in maintaining optimal canopy architecture through precise and timely pruning interventions. Conventional pruning practices rely heavily on operator expertise and subjective visual assessment, leading to inconsistent canopy management, suboptimal light distribution, and inefficient labor utilization. This review examines the emerging integration of augmented reality (AR) technologies as decision-support tools for precision pruning in high-density orchards, focusing on system architecture, sensor integration, and human-machine interaction paradigms. AR-assisted pruning systems combine real-time canopy sensing, three-dimensional plant reconstruction, computer vision algorithms, and spatially registered visual overlays to guide operators through optimized cutting decisions at the individual branch level. Key technological components include wearable and handheld AR display devices, depth-sensing cameras, inertial measurement units, and intelligent pruning recommendation engines based on physiological models and historical yield data. Field deployment studies demonstrate potential improvements in canopy uniformity, light interception efficiency, and operator training acceleration, though challenges remain in environmental robustness, computational performance, and system scalability. This article synthesizes current AR hardware platforms, algorithmic frameworks, and field validation results while identifying critical research gaps and pathways toward commercial adoption in precision orchard management.

BackgroundSearching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more than 25 years. It is based on a dynamic programming approach that explores all the possible alignments between two sequences; as a result it returns the optimal local alignment. Unfortunately, the computational cost is very high, requiring a number of operations proportional to the product of the length of two sequences. Furthermore, the exponential growth of protein and DNA databases makes the Smith-Waterman algorithm unrealistic for searching similarities in large sets of sequences. For these reasons heuristic approaches such as those implemented in FASTA and BLAST tend to be preferred, allowing faster execution times at the cost of reduced sensitivity. The main motivation of our work is to exploit the huge computational power of commonly available graphic cards, to develop high performance solutions for sequence alignment.ResultsIn this paper we present what we believe is the fastest solution of the exact Smith-Waterman algorithm running on commodity hardware. It is implemented in the recently released CUDA programming environment by NVidia. CUDA allows direct access to the hardware primitives of the last-generation Graphics Processing Units (GPU) G80. Speeds of more than 3.5 GCUPS (Giga Cell Updates Per Second) are achieved on a workstation running two GeForce 8800 GTX. Exhaustive tests have been done to compare our implementation to SSEARCH and BLAST, running on a 3 GHz Intel Pentium IV processor. Our solution was also compared to a recently published GPU implementation and to a Single Instruction Multiple Data (SIMD) solution. These tests show that our implementation performs from 2 to 30 times faster than any other previous attempt available on commodity hardware.ConclusionsThe results show that graphic cards are now sufficiently advanced to be used as efficient hardware accelerators for sequence alignment. Their performance is better than any alternative available on commodity hardware platforms. The solution presented in this paper allows large scale alignments to be performed at low cost, using the exact Smith-Waterman algorithm instead of the largely adopted heuristic approaches.

Despite significant advances in bioprinting technology, current hardware platforms lack the capability for process monitoring and quality control. This limitation hampers the translation of the technology into industrial GMP-compliant manufacturing settings. As a key step towards a solution, we developed a novel bioprinting platform integrating a high-resolution camera forin-situmonitoring of extrusion outcomes during embedded bioprinting. Leveraging classical computer vision and image analysis techniques, we then created a custom software module for assessing print quality. This module enables quantitative comparison of printer outputs to input points of the computer-aided design model's 2D projections, measuring area and positional accuracy. To showcase the platform's capabilities, we then investigated compatibility with various bioinks, dyes, and support bath materials for both 2D and 3D print path trajectories. In addition, we performed a detailed study on how the rheological properties of granular support hydrogels impact print quality during embedded bioprinting, illustrating a practical application of the platform. Our results demonstrated that lower viscosity, faster thixotropy recovery, and smaller particle sizes significantly enhance print fidelity. This novel bioprinting platform, equipped with integrated process monitoring, holds great potential for establishing auditable and more reproducible biofabrication processes for industrial applications.