Experimental Demonstration of Capacitive in‐Memory Computing Using Ferroelectric HZO Memcapacitors

A nonvolatile SRAM has been designed and fabricated by integrating with ferroelectric HfO2 capacitors, and its store/recall operation before/after power-off have been experimentally demonstrated. Excellent ferroelectricity and memory characteristics have been obtained in sub-10nm-thick ferroelectric HfO2 capacitor. The NVSRAM with ferroelectric HfO2 capacitor can be a candidate for cost-effective, normally-off and ultralow power embedded memory solution for IoT power management. Introduction IoT edge devices have been playing key roles as sensor node device. The number of IoT edge devices is predicted to be trillions or even more, and then obviously the device must operate at ultralow power in the order of 1mW or less [1]. IoT edge device operates in an intermittent mode where the switching times of a transistor per second is very small in average. Then the power consumption is dominated by standby leakage current especially in high capacity memory such as SRAM. Therefore it is very important to suppress leakage current of a memory cell. One possible approach is to turn off power supply for memory cells. To do so, state information must be stored and recalled, before and after power-off, so that latency and power overhead are mitigated. This is so called normally-off computing and low power nonvolatile memory needs to be integrated to SRAM, which turns out to be nonvolatile SRAM (NVSRAM) [2-4]. There are several architectures for NVSRAM. Ferroelectric NVSRAM has an advantage of low voltage and low power operation [4]. However, conventional ferroelectric material has several issues in CMOS compatibility and scaling. Recently, ferroelectricity has been discovered in HfO2 thin film which is already used in CMOS process as a high-k dielectric [5-7]. Ferroelectric HfO2 opens new paths for ferroelectric-based low power devices including NVSRAM. In this paper, NVSRAM is designed and fabricated by integrating ferroelectric HfO2 in our university lab. We focus on functional device implementation as a proof-of-concept for normally-off computing and IoT power management. Device Operation and Design Consideration In this work, among several ferroelectric NVSRAM architectures [4,8-11], we chose 6T-2C NVSRAM architectures (Fig.1) [4] because of its simple structure, operation principle, and above all its simple process integration with ferroelectric HfO2 capacitor. NVSRAM cell is made of 6T SRAM cell and two ferroelectric capacitors at the SRAM nodes. Bottom electrodes of ferroelectric capacitors are connected to plate line (PL). NVSRAM operates just as normal SRAM with PL is VDD/2. It only needs to flip ferroelectric polarization during store operation before power-off, which mitigates reliability requirement of ferroelectric capacitors. One of the most critical operations is recall. The nodes have opposite polarizations and thus different capacitances. The recall operation makes use of this capacitance imbalance to regenerate node voltages. Capacitor size and voltage ramp rate need to be carefully chosen. We confirmed recall operation in our NVSRAM design by SPICE simulation which was calibrated by our MOSFET and MIM capacitor. Experiments and Discussions NVSRAM was fabricated by following process flow. First SRAM was fabricated by conventional SOI CMOS process. After contact formation, bottom TiN/Ti electrode was deposited by sputtering. Then HfO2 doped with Zr was deposited by ALD system, followed by top TiN electrode deposition by sputtering. MIMS capacitor was formed by simple subtractive etching process. Lastly, RTA was performed to crystalize the HfO2 film. Fig. 2 shows the cross sectional TEM image of the ferroelectric HfO2 capacitor, where we confirmed uniformly crystallized 9nm-thick HfO2 thin film. PV characteristics of the MIM capacitor integrated on SRAM cell does not show any degradation as shown in Fig. 3. We also confirmed sufficient capacitance difference for each polarization state. From retention measurement, more than 1 year retention is estimated. Measured endurance cycle was 1x108 which is close to requirement for IoT power management, 1x109. NVSRAM cell shows no difference in static SRAM butterfly curve from reference SRAM cell on the same chip. Fig. 4 shows the measured waveform of the entire NVSRAM operation. First, data was written in normal SRAM mode, and then store operation was performed before power-off. After arbitrary sleep time, recall operation was performed and the written data was verified. We confirmed correct store and recall operation in NVSRAM and demonstrated nonvolatile functionality with ferroelectric HfO2 capacitors. Summary We experimentally demonstrated the nonvolatile functionality of the NVSRAM integrated with ferroelectric HfO2 capacitor fabricated in the university lab. NVSRAM will enable normally-off computing for IoT power management at low cost. In this work, we focused on demonstrating essential store/recall operations. Design optimization for high density and high speed operation using relevant CMOS technology will be our future work. Figure 1

Due to the voltage driven switching at low voltages combined with nonvolatility of the achieved polarization state, ferroelectric materials have a unique potential for low power nonvolatile electronic devices. The competitivity of such devices is hindered by compatibility issues of well-known ferroelectrics with established semiconductor technology. The discovery of ferroelectricity in hafnium oxide changed this situation. The natural application of nonvolatile devices is as a memory cell. Nonvolatile memory devices also built the basis for other applications like in-memory or neuromorphic computing. Three different basic ferroelectric devices can be constructed: ferroelectric capacitors, ferroelectric field effect transistors and ferroelectric tunneling junctions. In this article first the material science of the ferroelectricity in hafnium oxide will be summarized with a special focus on tailoring the switching characteristics towards different applications.The current status of nonvolatile ferroelectric memories then lays the ground for looking into applications like in-memory computing. Finally, a special focus will be given to showcase how the basic building blocks of spiking neural networks, the neuron and the synapse, can be realized and how they can be combined to realize neuromorphic computing systems. A summary, comparison with other technologies like resistive switching devices and an outlook completes the paper.

The rapid progress in artificial intelligence (AI) is driving the need for more efficient computing architectures capable of performing the demanding, repetitive computations required for processing large datasets. Unlike traditional von Neumann architectures, which separate processing and memory units, new approaches aim to integrate computational capabilities directly into memory arrays, facilitating in-memory computing (IMC). This integration significantly improves both energy efficiency and processing speed, particularly for AI and similar applications. A crucial operation within IMC is vector-matrix multiplication (VMM), where input signal vectors interact with a memory state matrix to produce output signal vectors.One innovative approach to implementing VMM is through the use of a ferroelectric Hf₀.₅Zr₀.₅O₂ (HZO) layer in conventional field-effect transistor (FET) or metal-insulator-metal (MIM) devices. These HZO-based ferroelectric components show significant promise for low-power, IMC-compatible systems, especially when integrated into MIM capacitor structures. Their simple fabrication process supports scalable system integration, while offering benefits such as low power consumption and high reliability. However, current IMC techniques utilizing ferroelectric MIM capacitors rely on small-signal capacitance readout, which suffers from limited contrast between high and low capacitance states, making it difficult to distinguish memory states effectively for efficient IMC operations.In this study, we introduce two novel readout techniques to improve the scalability and robustness of IMC, focusing on enhanced memory differentiation by reading the ferroelectric remanent polarization (Pᵣ) instead of relying on small-signal capacitance. These methods exploit the switching behavior between two stable polarization states (Pₗₒʷ and Pᵤₚ) of the HZO material. To measure charge accumulation resulting from polarization switching, we connect the ferroelectric HZO capacitors in series with either a shunt resistor (Rₛₕᵤₙₜ) or an external capacitor (Cₑₓt) to produce current or voltage signals, respectively. Both readout methods show significantly improved memory differentiation and VMM performance compared to the traditional small-signal capacitance approach. For example, in the current readout method, the maximum displacement current in the high-current state (Iₛʷ + Iₙₒₙ-ˢʷ) is approximately 0.31 mA, while the low-current state (Iₙₒₙ-ˢʷ) is about 0.04 mA when no switching current is present. Notably, the static leakage current during the input pulse is nearly zero, underscoring the potential for low-power operation in capacitive systems. In the voltage readout method, an initial Pᵤₚ state leads to a high output voltage (Vₒᵤₜ) of approximately 0.13 V, while an initial Pₗₒʷ state produces a low Vₒᵤₜ of about 0 V. These polarization-based readout techniques provide substantially higher memory distinction and better VMM performance compared to traditional small-signal capacitance methods.We will demonstrate IMC systems by using voltage readout of the Pr change in HZO layers, employing charge compensation between the Cext and HZO capacitors. This method takes advantage of the superior memory distinction within the capacitive system, offering more reliable and lower-power performance compared to traditional Fe-FET approaches.The authors acknowledge Prof. Joseph S. Friedman and Dr. Peng Zhou for the technical discussion.

Capacitive crossbar array with non-volatile ferroelectric capacitors as synaptic devices is designed and analyzed. We developed Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) based ferroelectric capacitors that exhibit tunable and non-volatile small-signal capacitance states. We claim that the capacitive crossbar architecture can perform read-disturbance-free and energy-efficient in-memory computing. In this paper, we first show the device characteristics and discuss the underlying physical mechanism. Moving to the array analysis, we identify the optimal ratio between reference capacitors (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> ) and ferroelectric capacitors (CFE) to maximize the output voltage swing >50 mV. Then we explore the tradeoff between delay and output switching and aim for delay <; 30ns. Based on the extracted experimental data from HZO capacitor and the array-level SPICE simulation, we show that a 128×128 non-volatile capacitive crossbar array is compatible with 3-bit analog-to-digital converter (ADC) for partial sum quantization even under thermal noise. The optimized capacitive crossbar design can achieve 3.8 pJ per vector-matrix multiplication, which is 14.3×~57.3× lower energy consumption compared to the representative resistive crossbar array.

Resistive random-access memory (RRAM) devices that can execute logic are promising for in-memory computing. In state-of-the-art, a complementary resistive switch (CRS) bit-cell of two back-to-back bipolar RRAM shows a universal logic gate by multiple sequential write/compute operations using a resistance-based input/output (R-R logic) along with an extra read cycle. Here, we propose and experimentally demonstrate a three-terminal RRAM (3T-RRAM) to enable logic operations with voltage input and resistance output (V-R logic) in a single device and single write/compute cycle without a dedicated read cycle. Essentially, a nanoscale (~20nm) side-contact is added to a typical two-terminal Pt/Pr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ca <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> MnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (PCMO)/W RRAM. As the PCMO RRAM is non-filamentary, all the terminals can act as in-out terminals. Hence, we utilize the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> terminal to read the state of the device while the other two terminals simultaneously performing the logic operation. Finally, we demonstrate the Implication (IMP) and converse IMP logic operations using 3T-RRAM. Such a device can enable area and energy-efficient in-memory computation.

Spiking neural networks (SNN) are computational models inspired by the brain’s ability to naturally encode and process information in the time domain. The added temporal dimension is believed to render them more computationally efficient than the conventional artificial neural networks, though their full computational capabilities are yet to be explored. Recently, in-memory computing architectures based on non-volatile memory crossbar arrays have shown great promise to implement parallel computations in artificial and spiking neural networks. In this work, we evaluate the feasibility to realize high-performance event-driven in-situ supervised learning systems using nanoscale and stochastic analog memory synapses. For the first time, the potential of analog memory synapses to generate precisely timed spikes in SNNs is experimentally demonstrated. The experiment targets applications which directly integrates spike encoded signals generated from bio-mimetic sensors with in-memory computing based learning systems to generate precisely timed control signal spikes for neuromorphic actuators. More than 170,000 phase-change memory (PCM) based synapses from our prototype chip were trained based on an event-driven learning rule, to generate spike patterns with more than 85% of the spikes within a 25 ms tolerance interval in a 1250 ms long spike pattern. We observe that the accuracy is mainly limited by the imprecision related to device programming and temporal drift of conductance values. We show that an array level scaling scheme can significantly improve the retention of the trained SNN states in the presence of conductance drift in the PCM. Combining the computational potential of supervised SNNs with the parallel compute power of in-memory computing, this work paves the way for next-generation of efficient brain-inspired systems.

Conventional processing of sensory input often relies on uniform sampling leading to redundant information and unnecessary resource consumption throughout the entire processing pipeline. Neuromorphic computing challenges these conventions by mimicking biology and employing distributed event-based hardware. Based on the task of lateral auditory sound source localization (SSL), we propose a generic approach to map biologically inspired neural networks to neuromorphic hardware. First, we model the neural mechanisms of SSL based on the interaural level difference (ILD). Afterward, we identify generic computational motifs within the model and transform them into spike-based components. A hardware-specific step then implements them on neuromorphic hardware. We exemplify our approach by mapping the neural SSL model onto two platforms, namely the IBM TrueNorth Neurosynaptic System and SpiNNaker. Both implementations have been tested on synthetic and real-world data in terms of neural tunings and readout characteristics. For synthetic stimuli, both implementations provide a perfect readout (100% accuracy). Preliminary real-world experiments yield accuracies of 78% (TrueNorth) and 13% (SpiNNaker), RMSEs of 41∘ and 39∘, and MAEs of 18∘ and 29∘, respectively. Overall, the proposed mapping approach allows for the successful implementation of the same SSL model on two different neuromorphic architectures paving the way toward more hardware-independent neural SSL.

The recent discovery of ferroelectricity in pure ZrO2 has drawn much attention, but the information storage and processing performances of ferroelectric ZrO2-based nonvolatile devices remain open for further exploration. Here, a ZrO2 (∼8 nm)-based ferroelectric capacitor using RuO2 oxide electrodes is fabricated, and the ferroelectric orthorhombic phase evolution under electric field cycling is studied. A ferroelectric remnant polarization (2Pr) of >30 μC/cm2, leakage current density of ∼2.79 × 10-8 A/cm2 at 1 MV/cm, and estimated polarization retention of >10 years are achieved. When the ferroelectric capacitor is connected with a transistor, a memory window of ∼0.8 V and eight distinct states can be obtained in such a ferroelectric field-effect transistor (FeFET). Through the conductance manipulation of the FeFET, a high object image recognition accuracy of ∼93.32% is achieved on the basis of the CIFAR-10 dataset in the convolutional neural network (CNN) simulation, which is close to the result of ∼94.20% obtained by floating-point-based CNN software. These results demonstrate the potential of ferroelectric ZrO2 devices for nonvolatile memory and artificial neural network computing.

We investigated the feasibility of the non-volatile operation of the III-V/Si hybrid SIS optical phase shifter with the series connection of a ferroelectric HZO capacitor. Thanks to ferroelectric polarization, non-volatile effective refractive index change can memorize the resonance or interference wavelength under zero bias.

Spin-based computing, combining logic and nonvolatile magnetic memory, is promising for emerging information technologies. However, the realization of a universal spin logic operation, representing a reconfigurable building block with all-electrical spin-current communication, has so far remained challenging. Here, we experimentally demonstrate reprogrammable all-electrical multifunctional spin logic operations in a nanoelectronic device architecture, utilizing graphene buses for spin communication and mixing and nanomagnets for writing and reading information at room temperature. This device realizes a multistate spin-majority logic operation, which is reconfigured to achieve (n)and, (n)or, and xnor Boolean operations, depending on the magnetization of inputs. The results are in good agreement with the predictions from a spin-circuit model, providing an experimental demonstration of a spin-based logic unit that takes advantage of the vector nature of spin, as opposed to conventional scalar charge-based devices. These spin logic operations in large-area graphene are fully compatible with industrial fabrication processes and represent a promising platform for scalable all-electric spin-based logic-in-memory computing architecture.

We have investigated the basic operation of a ferroelectric gate field-effect transistor (F-FET) memory with an intermediate electrode for data writing, using a discrete circuit which consists of a polycrystalline ferroelectric capacitor connected serially to the gate of a commercial n-channel metal–oxide–semiconductor (MOSFET). By sputtering, a ferroelectric capacitor Cf was formed as a (RuO2 top electrode)/poly-Pb(Zr0.52Ti0.48)O3(PZT)/(Pt/RuO2 bottom electrode) structure on a SiO2/Si substrate. The readout characteristics showed nondestructive operation. It was also shown that the output voltage for the positive and the negative polarization memory states corresponded very well with the intermediate electrode voltages on the gate of the MOSFET. Furthermore, the ratio of the ferroelectric capacitor to the input capacitor of the MOSFET was found to be an important factor influencing the cycle number of nondestructive reading and the difference in output voltage between the positive and negative polarization states.

Neuromorphic hardware that emulates biological computations is a key driver of progress in AI. For example, memristive technologies, including chalcogenide-based in-memory computing concepts, have been employed to dramatically accelerate and increase the efficiency of basic neural operations. However, powerful mechanisms such as reinforcement learning and dendritic computation require more advanced device operations involving multiple interacting signals. Here we show that nano-scaled films of chalcogenide semiconductors can perform such multi-factor in-memory computation where their tunable electronic and optical properties are jointly exploited. We demonstrate that ultrathin photoactive cavities of Ge-doped Selenide can emulate synapses with three-factor neo-Hebbian plasticity and dendrites with shunting inhibition. We apply these properties to solve a maze game through on-device reinforcement learning, as well as to provide a single-neuron solution to linearly inseparable XOR implementation.

Purpose: The objective of this research was to develop a sensor device to control and evaluate the jumping ability of elite volleyball athletes and to test its efficacy in a pedagogical experiment. Methods: The study involved determining the pulsometric and respiratory parameters during test loads, indicative of the endurance and speed-strength aspects essential for volleyball performance. Additionally, the necessity for post-training and post-competition jump performance restoration via short-term relaxation exercises was identified. Results: Through the developed computer program, a method for storing maximal vertical jumps in computer memory was established. Furthermore, a technique was developed to determine the functional significance of maximum vertical jump performance among elite volleyball players. Notably, participants in the experimental group, who performed specialized exercises developed within the experimental framework, exhibited discernible progressive improvements compared to the control group participants. Before the experiment, the maximum number of jumps in the experimental group was 29.2 ± 2.73, with a jump time of 31.7 ± 3.08. Conclusions: The equipment developed for monitoring and assessing volleyball players' jumping ability has proven effective, warranting its incorporation into training regimens.

In-Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrix-vector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMC-based PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43&#x0025;, close to floating-point implementation. Our simulations indicate a 250&#x00D7; improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.

Graph Neural Networks (GNNs) have emerged as a powerful framework for processing irregular, complex systems such as social networks and knowledge graphs. However, the inherent structural complexity of graphs imposes significant memory and computational overhead. These challenges are exacerbated by the traditional von Neumann architecture, where physically separated memory and processing units lead to substantial data movement bottlenecks. Consequently, in-memory computing (IMC) paradigms—specifically those leveraging memristor crossbar arrays—have become increasingly vital. While extensive research has focused on utilizing memristor arrays as weight layers for neural network acceleration, the adjacency matrix—a fundamental component representing graph topology—remains largely unimplemented in hardware. In this work, we provide the first experimental demonstration of a GNN architecture where the adjacency matrix is physically realized using a memristor crossbar array, harnessing its massive parallel computing capabilities. By integrating this hardware-based adjacency matrix with software-defined layers, we successfully implement digital image processing and resolve complex combinatorial optimization problems. Our results exhibit significantly enhanced computational efficiency and underscore the potential of memristor arrays as core components in GNN acceleration. This physical implementation of the adjacency matrix expands the horizons of memristor-based neuromorphic computing systems, offering a scalable path toward high-performance machine learning and artificial intelligence hardware.