Ferroelectric Hf0.5Zr0.5O2 Memcapacitor Array for in-Memory Computing

A nonvolatile SRAM has been designed and fabricated by integrating with ferroelectric HfO2 capacitors, and its store/recall operation before/after power-off have been experimentally demonstrated. Excellent ferroelectricity and memory characteristics have been obtained in sub-10nm-thick ferroelectric HfO2 capacitor. The NVSRAM with ferroelectric HfO2 capacitor can be a candidate for cost-effective, normally-off and ultralow power embedded memory solution for IoT power management. Introduction IoT edge devices have been playing key roles as sensor node device. The number of IoT edge devices is predicted to be trillions or even more, and then obviously the device must operate at ultralow power in the order of 1mW or less [1]. IoT edge device operates in an intermittent mode where the switching times of a transistor per second is very small in average. Then the power consumption is dominated by standby leakage current especially in high capacity memory such as SRAM. Therefore it is very important to suppress leakage current of a memory cell. One possible approach is to turn off power supply for memory cells. To do so, state information must be stored and recalled, before and after power-off, so that latency and power overhead are mitigated. This is so called normally-off computing and low power nonvolatile memory needs to be integrated to SRAM, which turns out to be nonvolatile SRAM (NVSRAM) [2-4]. There are several architectures for NVSRAM. Ferroelectric NVSRAM has an advantage of low voltage and low power operation [4]. However, conventional ferroelectric material has several issues in CMOS compatibility and scaling. Recently, ferroelectricity has been discovered in HfO2 thin film which is already used in CMOS process as a high-k dielectric [5-7]. Ferroelectric HfO2 opens new paths for ferroelectric-based low power devices including NVSRAM. In this paper, NVSRAM is designed and fabricated by integrating ferroelectric HfO2 in our university lab. We focus on functional device implementation as a proof-of-concept for normally-off computing and IoT power management. Device Operation and Design Consideration In this work, among several ferroelectric NVSRAM architectures [4,8-11], we chose 6T-2C NVSRAM architectures (Fig.1) [4] because of its simple structure, operation principle, and above all its simple process integration with ferroelectric HfO2 capacitor. NVSRAM cell is made of 6T SRAM cell and two ferroelectric capacitors at the SRAM nodes. Bottom electrodes of ferroelectric capacitors are connected to plate line (PL). NVSRAM operates just as normal SRAM with PL is VDD/2. It only needs to flip ferroelectric polarization during store operation before power-off, which mitigates reliability requirement of ferroelectric capacitors. One of the most critical operations is recall. The nodes have opposite polarizations and thus different capacitances. The recall operation makes use of this capacitance imbalance to regenerate node voltages. Capacitor size and voltage ramp rate need to be carefully chosen. We confirmed recall operation in our NVSRAM design by SPICE simulation which was calibrated by our MOSFET and MIM capacitor. Experiments and Discussions NVSRAM was fabricated by following process flow. First SRAM was fabricated by conventional SOI CMOS process. After contact formation, bottom TiN/Ti electrode was deposited by sputtering. Then HfO2 doped with Zr was deposited by ALD system, followed by top TiN electrode deposition by sputtering. MIMS capacitor was formed by simple subtractive etching process. Lastly, RTA was performed to crystalize the HfO2 film. Fig. 2 shows the cross sectional TEM image of the ferroelectric HfO2 capacitor, where we confirmed uniformly crystallized 9nm-thick HfO2 thin film. PV characteristics of the MIM capacitor integrated on SRAM cell does not show any degradation as shown in Fig. 3. We also confirmed sufficient capacitance difference for each polarization state. From retention measurement, more than 1 year retention is estimated. Measured endurance cycle was 1x108 which is close to requirement for IoT power management, 1x109. NVSRAM cell shows no difference in static SRAM butterfly curve from reference SRAM cell on the same chip. Fig. 4 shows the measured waveform of the entire NVSRAM operation. First, data was written in normal SRAM mode, and then store operation was performed before power-off. After arbitrary sleep time, recall operation was performed and the written data was verified. We confirmed correct store and recall operation in NVSRAM and demonstrated nonvolatile functionality with ferroelectric HfO2 capacitors. Summary We experimentally demonstrated the nonvolatile functionality of the NVSRAM integrated with ferroelectric HfO2 capacitor fabricated in the university lab. NVSRAM will enable normally-off computing for IoT power management at low cost. In this work, we focused on demonstrating essential store/recall operations. Design optimization for high density and high speed operation using relevant CMOS technology will be our future work. Figure 1

Capacitive crossbar array with non-volatile ferroelectric capacitors as synaptic devices is designed and analyzed. We developed Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) based ferroelectric capacitors that exhibit tunable and non-volatile small-signal capacitance states. We claim that the capacitive crossbar architecture can perform read-disturbance-free and energy-efficient in-memory computing. In this paper, we first show the device characteristics and discuss the underlying physical mechanism. Moving to the array analysis, we identify the optimal ratio between reference capacitors (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</sub> ) and ferroelectric capacitors (CFE) to maximize the output voltage swing >50 mV. Then we explore the tradeoff between delay and output switching and aim for delay <; 30ns. Based on the extracted experimental data from HZO capacitor and the array-level SPICE simulation, we show that a 128×128 non-volatile capacitive crossbar array is compatible with 3-bit analog-to-digital converter (ADC) for partial sum quantization even under thermal noise. The optimized capacitive crossbar design can achieve 3.8 pJ per vector-matrix multiplication, which is 14.3×~57.3× lower energy consumption compared to the representative resistive crossbar array.

Ferroelectricity exhibits two stable states with permanent polarizations, making it promising for nonvolatile memory applications. Compared to conventional perovskite ferroelectrics, hafnium-based ferroelectric materials, such as Hf0.5Zr0.5O2 (HZO), attracts much attention due to their compatibility with CMOS technology [1]. Furthermore, with the high demand in high-performance computing and the emerging quantum computing, cryogenic memory technologies become more important due to the required much lower operational temperatures. In this work, we investigate the properties of HZO-based ferroelectric capacitors and characterize ferroelectric field-effect transistors (FeFETs) from 300 K to 4 K.A 10-nm HZO layer was deposited by atomic layer deposition (ALD) to serve as the ferroelectric layer in both capacitors and FeFETs (Fig. 1). For the ferroelectric capacitors, 75-nm TiN was deposited by sputtering for the bottom and top electrodes, which provides tensile stress to the HZO layer and facilitates the formation of the ferroelectric phase [2]. Similarly, in FeFETs, a 75-nm TiN is deposited as the gate metal. Subsequent rapid thermal annealing (RTA) steps were performed at 650 °C for 30 seconds in forming gas to form the ferroelectric orthorhombic phase. For the FeFETs, different gate stacks were deposited: a 10-nm HZO layer (MFS structure) or a combination of a 10-nm HZO layer and a 1-nm Al2O3 interlayer (IL) between the HZO and the Si substrate to improve the interface quality (MFIS structure).For ferroelectric capacitors, the polarization vs. voltage (P-V) results are measured at temperatures from 300 K to 4 K (Fig. 2(a)). The extracted remnant polarization (2Pr) and coercive voltage (2Vc) are shown in Fig. 2(b). 2Pr value decreases with a reducing temperature due to the reduced mobility of oxygen vacancies, leading to weaker polarizations in cryogenic environments [3]. 2Vc increases with a decreasing temperature, which means that a higher voltage is required to switch the polarization direction at lower temperatures [4]; that is, polarization switching becomes more challenging.MFS and MFIS FeFETs were also characterized at 300 K to 4 K. The Id-Vg results with various gate sweeping ranges of MFS and MFIS FeFETs at 300 K are shown in Fig. 3. We observed a competition between ferroelectric polarization switching (counter-clockwise Id-Vg hysteresis loops) and charge trapping effects (clockwise Id-Vg hysteresis loops). To further analysis, we define the required gate bias with zero hysteresis (Vsweep at ΔVth = 0) as the voltage where ferroelectricity starts to dominate. For MFIS FeFETs, the required sweep bias is larger than that of MFS FeFETs, which suggests that a higher applied voltage is needed to switch the dipoles in MFIS FeFETs. This is because a portion of the applied voltage drops across the IL, thereby decreasing the electric field in the ferroelectric layer. Furthermore, there’s an internal depolarization field induced by Al2O3 IL, which opposes the polarization in the ferroelectric layer and reduces its polarization [5]. As the scan range of gate bias becomes larger, MFS FeFETs exhibit stronger ferroelectricity (counter-clockwise hysteresis with a negative ΔVth) (Fig. 4(a)). As the temperature decreases, the required scan range of gate biases becomes much larger, which makes the HZO films more difficult to convert to ferroelectric phases. In contrast, MFIS FeFET shows counter-clockwise hysteresis only at 300 K (Fig. 4(b)), below which charge trapping effects dominate over polarization switching even under a sweep voltages up to 5 V. This trend is consistent with the results in ferroelectric capacitors, where higher voltages are required for polarization switching at lower temperatures. Acknowledgements This work was supported by the Powerchip Semiconductor Manufacturing Corporation (PSMC) of Taiwan (grant No: 113H1004-C15), the National Science and Technology Council (NSTC 113-2119-M-002-022-), and the Center of Data Intelligence: Technologies, Applications, and Systems, National Taiwan University (grant No: 113L900903). References Müller et al., IEDM, 10.8 (2013).Si Joon Kim et al., Appl. Phys. Lett. 111, 242901 (2017).Starschich et al., Appl. Phys. Lett. 108, 032903 (2016).Stephen Ducharme et al., Phys. Rev. Lett. 84, 175 (2000).Patrick D. Lomenzo et al., Non-Volatile Memory Technol. Symp., 1 (2019). Figure 1

Abstract. Ferroelectric Hf0.5Zr0.5O2 (HZO) exhibits grain-size-dependent polarization switching that dominates variability in FeFET neuromorphic crossbars, yet the quantitative link from microstructure to array-level accuracy remains unexplored. This work bridges polycrystalline grain physics to 64×64 array performance via our proposed grain count conditioned surrogate, GrainAwareNet, developed using a 2D cross-sectional phase-field model assuming columnar grain structure typical of thin HZO films. Simulations yield 1,927 valid P-E loops spanning grain counts G = 10-100 (equivalent mean grain size ~6-19 nm), with Pr = 15-35 µC/cm² (±15%) and Ec = 80-180 MV/m (±40%). GrainAwareNet achieves R² = 0.9923, RMSE = 0.032 µC/cm², and 1000× speedup, enabling Monte Carlo exploration of grain-count variability σG = 0-40. The framework demonstrates remarkable robustness: Matrix-Vector Multiply (MVM) output error remains &lt;1% for σG up to ~35, with &lt;0.3% error at σG = 5 (CV &lt; 6%). Voltage calibration further recovers ~90% accuracy at higher variability. Framework enables microstructure-aware design-technology co-optimization (DTCO) for HZO FeFETs.

Due to the voltage driven switching at low voltages combined with nonvolatility of the achieved polarization state, ferroelectric materials have a unique potential for low power nonvolatile electronic devices. The competitivity of such devices is hindered by compatibility issues of well-known ferroelectrics with established semiconductor technology. The discovery of ferroelectricity in hafnium oxide changed this situation. The natural application of nonvolatile devices is as a memory cell. Nonvolatile memory devices also built the basis for other applications like in-memory or neuromorphic computing. Three different basic ferroelectric devices can be constructed: ferroelectric capacitors, ferroelectric field effect transistors and ferroelectric tunneling junctions. In this article first the material science of the ferroelectricity in hafnium oxide will be summarized with a special focus on tailoring the switching characteristics towards different applications.The current status of nonvolatile ferroelectric memories then lays the ground for looking into applications like in-memory computing. Finally, a special focus will be given to showcase how the basic building blocks of spiking neural networks, the neuron and the synapse, can be realized and how they can be combined to realize neuromorphic computing systems. A summary, comparison with other technologies like resistive switching devices and an outlook completes the paper.

Deep learning architectures are increasingly limited by the memory wall — the “von Neumann bottleneck” that forces frequent data transfers between memory and processing units, throttling throughput and energy efficiency. To alleviate this bottleneck, researchers have explored Compute-in-Memory (CiM) architectures to accelerate the core computing primitives such as the matrix–vector multiplications (MVMs), within memory arrays. Yet, large language models based on transformers also require many non-linear softmax operations, creating a new bottleneck. From a technology perspective, non-volatile STT-MRAMs are promising for CiM thanks to their endurance, nonvolatility, and area footprint. However, conventional 1T–1R STT-MRAM CiM arrays place bit-cells in parallel, yielding lower MVM energy efficiency than 8T-SRAM CiM due to low device resistance; line parasitics and low OFF/ON ratios of STT-MRAM devices further limit row parallelism and scalability. In this context, we propose ROSETTA, a CiM array based on 3T–2R STT-MRAM bit-cells that uses series-resistance sensing and time-to-digital conversion (TDC) for low-power MVMs. An added word line also stores a ROM bit, enabling in-array tables for fast softmax, without increasing bit-cell area. We introduce a novel palindromic encoding of inputs and weights to mitigate the data-dependent nonlinearity in STT-MRAM CiM arrays based on TDC sensing. This enables 8× higher row-level parallelism than standard 1T–1R MRAM CiM and facilitates scaling to larger CiM arrays. Our macro occupies ∼ 47% less area and consumes 3.1× less MVM energy than an equivalent ROM-overlaid 8T-SRAM macro, at similar latency and accuracy. At the system level, a spatial architecture comprising our macros exhibits 11.7−14.5× and 1.44 − 1.5× higher energy efficiency than equivalent architectures comprising 1T-1R MRAM and 8T-SRAM ROM-overlaid CiM macros, respectively.

Ferroelectric capacitors (Fe‐Caps) exhibiting memcapacitive behavior are emerging as a compelling platform for low‐power capacitive in‐memory computing (IMC). Their inherently open‐circuit nature suppresses static current and sneak paths, offering a distinct advantage over resistive IMC counterparts. In this work, an experimental demonstration is presented of a cross‐point Fe‐Cap array prototype, establishing capacitive IMC with non‐destructive readout characteristics. The devices exhibit robust reliability, sustaining more than 10 5 read cycles and 10 7 write cycles, with retention projected beyond 10 years without memory collapse. At the system level, a 4 × 2 array achieves 100% accuracy in 2‐pixel × 2‐pixel pattern‐recognition tasks, while scaling to a 16 × 4 array and letter‐recognition tasks highlights the outstanding scalability of Fe‐Cap‐based IMC platforms. These results not only validate the Fe‐Caps as both a functional and reliable IMC element but also provide an experimental framework for straightforward evaluation of IMC functionality, marking a milestone toward practical and energy‐efficient neuromorphic hardware.

Conventional in-memory computing (IMC) architectures consist of analog memristive crossbars to accelerate matrix-vector multiplication (MVM), and digital functional units to realize nonlinear vector (NLV) operations in deep neural networks (DNNs). These designs, however, require energy-hungry signal conversion units which can dissipate more than 95% of the total power of the system. Fully-analog IMC circuits remove the need for signal converters by realizing both MVM and NLV operations in the analog domain leading to significant energy savings. However, they are more susceptible to errors caused by interconnect parasitic and noise. Here, we propose Xbar-partitioning, a practical approach to divide large IMC arrays into multiple partitions to alleviate the impacts of noise and parasitics while keeping the computation in the analog domain. The SPICE circuit simulation results for the deployment of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400\times 120\times 84\times 10$ </tex-math></inline-formula> DNN model on various fully-analog IMC architectures with five different 2-terminal and 3-terminal resistive devices, six different bitcell layouts, and four different partitioning schemes show that the highest accuracy of 98.08% can be obtained for a design using phase-change memory (PCM) devices and 1T-1R bitcell with 13, 4, and 3 horizontal partitions, and 4, 3, and 1 vertical partition for the first, second, and third layers of the DNN, respectively. Finally, we provide a signal-to-noise ratio (SNR) analysis which shows that the IMC architectures can be made more noise-tolerant by using smaller-sized bitcells, higher partitions in the crossbar, and device technologies with higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{off}/R_{on}$ </tex-math></inline-formula> ratio.

This study presents a theoretical investigation of the physical mechanisms governing small-signal capacitance in ferroelectrics, focusing on hafnium zirconium oxide (Hf0.5Zr0.5O2, HZO). We utilize a time-dependent Ginzburg-Landau formalism-based 2D multi-grain phase-field framework to simulate the capacitance of metal-ferroelectric-insulator-metal (MFIM) capacitors. Our simulation methodology closely mirrors the experimental procedures for measuring ferroelectric small-signal capacitance, and the outcomes replicate the characteristic butterfly capacitance-voltage behavior. Notably, this behavior can be obtained without invoking traps. We delve into the components of the ferroelectric capacitance associated with the dielectric response and polarization switching, discussing the primary mechanisms - domain bulk response and domain wall response - contributing to the butterfly characteristics. We explore their interplay and relative contributions to the capacitance, correlating them to the polarization switching mechanisms and domain configurations. Additionally, we investigate the impact of increasing domain density with ferroelectric thickness scaling, demonstrating an enhancement in the polarization capacitance component, in addition to the dielectric component. Furthermore, we analyze the contributions of the domain bulk and domain wall responses across ferroelectric thicknesses, relating the capacitive memory window (for memory applications) to the capacitance and revealing a non-monotonic dependence of the maximum memory window on the ferroelectric thickness.

This work proposes a static random access memory (SRAM)-based delta-sigma computing-in-memory (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM) processor for edge intelligence applications in 22-nm CMOS technology. This <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM processor effectively mitigates redundant operations associated with unchanged input features and adaptively adjusts computing-in-memory (CIM) outputs to achieve a near-zero-mean (NZM) distribution, thereby benefiting the energy-intensive analog-to-digital converters (ADCs). The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM macro involves three main innovations at the architecture and circuit levels: first, it replaces absolute inputs with deltas computed from consecutive input values, resulting in a notable 35.8% reduction in energy consumption for the CIM array; second, the delta matrix-vector multiplications (MVMs) implemented by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> CIM array can self-adaptively shift the analog CIM outputs to be NZM distributed, facilitating streamlined centralized data processing; and third, the introduction of a least significant bit first (LSB-first) ADC, whose number of conversions adjust dynamically based on instantaneous input values, allows for efficient analog output conversion of highly concentrated NZM analog data without compromising full-scale range or precision. Compared with state-of-the-art (SOTA) analog SRAM-based CIM macros, this work achieves superior area-energy efficiency product by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25{\times }$ </tex-math></inline-formula> with up to 21.38 TOPS/W and 1.44 TOPS/mm2 at full precision of 8b input, 8b weight, and 24b output, through bit-serial inputs and shifter-and-adder.

In-memory computing (IMC) is gaining momentum for low-power acceleration of data intensive problems, particularly in the frame of artificial intelligence (AI). Analogue matrix-vector multiplication (MVM) in crosspoint arrays allows to dramatically improve energy efficiency in neural networks for inference and training [1]. Recently, it has been shown that a feedback configuration of MVM can accelerate the solution of generic linear matrix problems, such as linear systems, matrix inversion and eigenvector calculation, with a single computational step [2,3]. This is achieved by the high parallelism of MVM in the memory array, combined with the physical iteration executed naturally in the feedback loop. Eigenvector extraction allows to address general problems, such as PageRank of internet webpages, with complexity O(1), i.e., the time to solve a ranking problem remains fixed irrespective of the size of the coefficient matrix [4]. In this work, we address two specific problems of AI acceleration, namely regression and optimization.Linear regression can be viewed as one of the most basic problems of machine learning: given a sequence of points, one must predict the value of the next point in the sequence. This problem can be solved in just one computational step by using the closed-loop crosspoint array of Fig. 1, where the independent variables x_i are physically written within the two crosspoint arrays, while the dependent variables y_i are applied externally as input currents. The crosspoint arrays are connected within a closed-loop configuration by using operational amplifiers (OAs) in the rows and the columns of the arrays. The OA output yields the coefficients of the best fitting line along the sequence, i.e., the coefficients a and b in the line equation y= ax + b providing the least mean squares (LMS) regression of the sequence. This problem can be extended to any arbitrary dimension, i.e., not only data on x-y plane, but also data on x-y-z space and any hyperspace of n dimensions. The problem can also be extended to logistic regression, which enables classification in one computational step. In particular, the crosspoint regression circuit allows the training of a 2-layer perceptron in just one step, by assuming random weights in the first layer according to the extreme learning machine (ELM) approach. In-memory computing thus appears as a promising option for accelerating neural network training with complexity O(1).The continuous-time, analogue closed-loop approach can be extended to a discrete-time, digital recurrent neural network (RNN) for addressing optimization problems [5]. The RNN allows the efficient solution of constraint satisfaction problems (CSPs), such as Sudoku, by taking advantage of analogue MVM in the crosspoint array. In the RNN, stochastic iterations can allow the minimization of the cost function, hence the number of violated constraints, thus leading to the global minimum. Noise can be injected as spike jitter by phase change memory devices as integrate-and-fire neurons. The convergence to the solution can be efficiently accelerated by a 2-layer RNN, where the first layer is programmed to prevent the violation of constraints in the CSP. In-memory solution of CSPs can dramatically improve the energy efficiency and speed of data intensive optimization in transport, industry, and society in general.

This paper introduces a GPU architecture named Duplo that minimizes redundant memory accesses of convolutions in deep neural networks (DNNs). Convolution is one of the fundamental operations used in various classes of DNNs, and it takes the majority of execution time. Various approaches have been proposed to accelerate convolutions via general matrix multiplication (GEMM), Winograd convolution, fast Fourier transform (FFT), etc. Recent introduction of tensor cores in NVIDIA GPUs particularly targets on accelerating neural network computations. A tensor core in a streaming multiprocessor (SM) is a specialized unit dedicated to handling matrix-multiply-and-accumulate (MMA) operations. The underlying operations of tensor cores represent GEMM calculations, and lowering a convolution can effectively exploit the tensor cores by transforming deeply nested convolution loops into matrix multiplication. However, lowering the convolution has a critical drawback since it requires a larger memory space (or workspace) to compute the matrix multiplication, where the expanded workspace inevitably creates multiple duplicates of the same data stored at different memory addresses. The proposed Duplo architecture tackles this challenge by leveraging compile-time information and microarchitectural supports to detect and eliminate redundant memory accesses that repeatedly load the duplicates of data in the workspace matrix. Duplo identifies data duplication based on memory addresses and convolution information generated by a compiler. It uses a load history buffer (LHB) to trace the recent load history of workspace data and their presence in register file. Every load instruction of workspace data refers to the LHB to find if potentially the same copies of data exist in the register file. If data duplicates are found, Duplo simply renames registers and makes them point to the ones containing the same values instead of issuing memory requests to load the same data. Our experiment results show that Duplo improves the performance of DNNs by 29.4% on average and saves 34.1% of energy using tensor cores.

Compute-in-memory (CiM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, the tradeoff between energy efficiency and computing precision plagues most CiM implementations, and the low precision imposes a major limitation on CiM’s ability to support practical computational workloads. In this article, a static random access memory (SRAM)-based analog CiM macro is presented with the Intel 22FFL process. By introducing a 1-to-2 ratioed capacitor ladder (C-2C)-based charge domain computing scheme, the proposed CiM prototype chip demonstrates a maximum of 2k multiply-accumulate (MAC) operations in one clock cycle and achieves 32.2-TOPS/W peak power efficiency with 8-bit precision in both input activation and weight while ensuring accurate on-chip matrix–vector multiplications (MVMs) with a computation error less than 0.5%. A 4.0-TOPS/mm2 peak area efficiency is attained by adopting a local weight multiplexing scheme with a 9T SRAM cell, which improves the memory density and reduces the need to refresh the weight stored in the SRAM array. A variety of analog impairment factors, including parasitics, mismatch, and noise, were analyzed to guarantee a sufficiently high multibit linearity. The proposed passive analog computing mechanism ensures the computation accuracy over process–voltage–temperature (PVT), with the measured MVM error deviation of less than 1% over PVT variations.

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices.

Data movement between memory and processing units poses an energy barrier to Von-Neumann-based architectures. In-memory computing (IMC) eliminates this barrier. RRAM-based IMC has been explored for data-intensive applications, such as artilicial neural networks and matrix-vector multiplications that are considered as “soft” tasks where performance is a more important factor than accuracy. In “hard” tasks such as partial differential equations (PDEs), accuracy is a determining factor. In this brief, we propose ReLOPE, a fully RRAM crossbar-based IMC to solve PDEs using the Runge-Kutta numerical method with 97% accuracy. ReLOPE expands the operating range of solution by exploiting shifters to shift input data and output data. ReLOPE range of operation and accuracy can be expanded by using line-grained step sizes by programming other RRAMs on the BL. Compared to software-based PDE solvers, ReLOPE gains 31.4× energy reduction at only 3% accuracy loss.