Exposing extreme ultraviolet lithography at Intel

Implementation of extreme ultra violet lithography (EUVL) for printing features of dimensions around 32nm and below has faced multiple challenges that have been overcome mostly through tool and process engineering. Currently, the main concern for implementation of EUVL in high volume manufacturing is related to stochastic defects, such as line bridges or breaks, which may occur randomly and have an impact on device performance.1 Photon shot noise, in addition to the inherent process variability and material non-homogeneities can lead to defects on the final patterned structures. As the pitch and critical dimension (CD) approach 32nm pitch and below, the dependency of stochastics defects increases exponentially. This paper fits within imec’s EUV stochastics and defectivity program, which investigates the key parameters for the generation and mitigation of defects from both a theoretical and practical approach. Initially, a reference process has been established and a methodology has been developed to capture and characterize bridge-type defects after pattern transfer into relevant layers for metrology and applications. Optical inspection and scanning electron microscopy (SEM) review are used to collect information on the number and types of defects present over large patterned areas (in the order of cm2). With a well-defined inspection technique, experiments related to fundamentals as well as materials and processes are continuously run. In the past years, imec has been leading the fundamental work on stochastic defects.2,3 De Bisschop et al. identified the “defect cliff”, or the exponential dependency of defect density as a function of space CD for multiple parameters, such as resist formulation and exposure/imaging conditions. More recently, the focus has changed to the investigation of the “defect floor”, which as the name suggests, is a flat response of defects to CD. The defect floor suggests that defectivity cannot be further improved, making one of the most relevant problems to solve for implementation of EUV in high volume manufacturing (HVM). Our results show a decomposition of the potential contributors to explore the effect of processing conditions related to scanner, track and pattern transfer on final defect density for a chemically amplified resist and attempt a comparison to a metal-oxide resist. Goal is to understand the contributors to the defect floor and identify an effective route to avoid/minimize defect formation.

Extreme ultraviolet (EUV) lithography has emerged as a promising candidate for the manufacturing of semiconductor devices at the sub-14nm half pitch lines and spaces (LS) pattern for 7 nm node and beyond. The success of EUV lithography for the high volume manufacturing of semiconductor devices depends on the availability of suitable resist with high resolution and sensitivity. It is well-known that the key challenge for EUV resist is the simultaneous requirement of ultrahigh resolution (R), low line edge roughness (L) and high sensitivity (S). In this paper, we investigated and developed new chemically amplified resist (CAR) materials to achieve sub-14 nm hp resolution. We found that both resolution and sensitivity were improved simultaneously by controlling acid diffusion length and efficien-cy of acid generation using novel PAG and sensitizer. EUV lithography evaluation results obtained for new CAR on Micro Exposure Tool (MET) and NXE3300 system are described and the fundamentals are discussed.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM) for preparing advanced semiconductor devices. That was very important year for EUV enthusiasts and semiconductor industry. Because it takes for a long time, more than 30 years, to study EUV lithography for realizing HVM. With recent rapid progress on the source power improvement, EUV lithography development including photoresist materials has been achieved HVM requirements. However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. One of the critical issues is the stochastic issues, which will be become ‘defectivity’, like a nano-bridge or a nano-pinching. The analyzing summary of the stochastic factors in EUV lithography, and their improvement status are described in this paper. 2 (two) major stochastic issues, which are photon stochastic and chemical stochastic, were observed in the lithography steps. And the improvement status of each stochastic issues including lithographic results are also described.

The following topics are dealt with: low-power electronics; Internet of Things; integrated circuit design; video coding; integrated circuit manufacture; CMOS integrated circuits; field programmable gate arrays; magnetic sensors; calibration; power consumption.

Extreme ultraviolet lithography (EUVL) is the leading technology for patterning at the 32 nm technology node and be-yond. EUVL light at 13.5 nm is used to print circuits. This light is produced by heating fuel (Xe, Sn) in EUV sources to a very high temperature by using either magnetic compression or laser irradiation. Today EUV source power remains the number one concern for implementation of EUVL in high volume manufacturing. Over the last few years, much pro-gress has been made in EUV source performance and availability. Today, alpha level high power (~10 W) EUV sources have been integrated in alpha level EUVL scanners. Medium and low power EUV sources are used for in-house metrol-ogy and performance studies on EUV mask blanks, EUV masks, photoresists, and optical elements. These compact dis-charge sources with medium power in the range of 10-100 mW/sr/2% bandwidth and low power EUV tubes are being used by various RD today, these low power EUV sources are instrumental in allowing in-house R&D projects. In this paper, the latest status of high power EUV sources, low and medium power metrology sources, and some of their appli-cations are described.

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 32nm half-pitch node and beyond. Readiness of EUV materials is currently one high risk area according to assessments made at the 2008 EUVL Symposium. The main development issue regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data is presented utilizing Intel's Micro-Exposure Tool (MET) examining the feasibility of establishing a resist process that simultaneously exhibits ≤30nm half-pitch (HP) L/S resolution at ≤10mJ/cm2 with ≤4nm LWR.

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. Readiness of EUV materials is currently one high risk area according to recent assessments made at the 2009 EUVL Symposium. The main development issue regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data collected utilizing Intel's Micro-Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤ 12.5mJ/cm2 with ≤ 4nm LWR.

Extreme-UV lithography (EUVL) is the most promising candidate of next generation technology for hp20nm node device manufacturing and beyond, however there are many critical issues to solve in the light source, tools, mask and photo resist. Regarding the development of a photo resist, it is necessary for high volume manufacturing (HVM) to improve LWR, resolution limit and sensitivity. Additionally, concerning about deterioration of a patterning performance by Out-of-Band (OoB) light existing in the EUV light, and contamination problem of exposure tool due to the photo resist outgassing are the key issues which have to be resolved toward HVM by EUVL. Especially, the outgassing problem can become a significant issue for fine patterning under high dose exposure condition. This paper proposes the novel solution for these critical issues with the application of a top coat material which is named OBPL (Outgassing & out-of-Band Protection Layer) on photo resist. The key characteristics of OBPL material are to have a role in protection against the OoB adverse effect to keep up the photo resist performance, to suppress the outgassing from photo resist as a barrier layer and to enhance the lithographic performance such as photo resist profile and process window. In designing the OBPL material, the optical property needs having not only the high absorbance of DUV (Deep-UV) light in OoB range but also high transmittance for 13.5nm wavelength to prevent the sensitivity loss. Furthermore, it is found that the polymer backbone affects the outgassing barrier capability in previous evaluation. Based on these investigations, a state-of-the-art OBPL achieves quite a positive lithographic result with sufficient OoB absorption and outgassing suppression. Moreover, this material has applicability to all types of photo resist including NTD (Negative-Tone Development) process. This paper describes the result of the feasibility study for OBPL and the lithography performance with EUV full field scanner.

While extreme ultraviolet lithography (EUVL) is the leading candidate of the next generation lithography, the challenge of managing blank defects must be overcome before EUVL being put to practical use. Besides the efforts of manufacturing defect free blanks, the use of mitigation technique called “pattern shift” is now considered to be a more feasible solution. Whether we aim for defect free blanks or use pattern shift, however, it is quite important to understand the properties of the defects on EUV masks. Of particular interest is to distinguish phase defects from amplitude defects, and pits from bumps. To address the need to understand defect properties, the Actinic Blank Inspection (ABI) high volume manufacturing (HVM) model has acquired a review function using a 1200x magnification optics capable of accurately measuring the size and shape of defects. In this paper, we will discuss how the ABI HVM model classifies defects into pits and bumps.

Intel's efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes as well as production-level process control. We present key device features and fabrication details as well as qubit characterization results confirming device functionality. These results corroborate our fabrication methods and are a crucial step toward scaling of extensible 2D qubit array schemes.

Debris mitigation is still a critical issue for the development of extreme ultraviolet projection lithography (EUVL). Here, we describe the analysis of the efficiency of the debris-mitigation system (DMS) presently in use in the laser–plasma–source micro-exposure tool (MET) operating at the Frascati ENEA Research Center. Basic to such an analysis is a code specifically developed for processing the images of debris-flux-exposed glass slides. The code stands out as a tool for further plasma debris-related analyses.

EUV lithography has the ability to support 22 nm logic (or 32nm half pitch) node and beyond. Similar to the DUV lithographic systems, partial coherence on EUV lithographic systems can have a big impact on process latitude for critical layers. Thus, it is important to understand the effect of partial coherence on EUV imaging systems. In this paper, process windows with various illumination settings are investigated. The experiments were done using the MET station at the Advance Light Source (ALS). The exposures were targeted for 60 nm, 50 nm, and 45 nm dense features. The outer and inner sigmas of annular illumination varied from 0.2 to 0.8. In addition, dipole, C-quad, and quad illuminations were used to explore the impact of the partial coherence on the process window. Knowledge gained can then be applied to verify lithography models and aid in future tool designs.

This work explores the application of alternative developer solutions (“developers”) with the aim of understanding their potential effectivity in the reduction of resist-based stochastic pattern defects (or “stochastic defects”) in extreme ultraviolet lithography (EUVL). Specifically, the application of a quaternary ammonium hydroxide type aqueous developer; ethyltrimethylammonium hydroxide (ETMAH) in comparison to the industry de facto standard aqueous alkali tetramethylammonium hydroxide (TMAH) developer was investigated. Focusing on EUV exposed contact hole (CH) patterns on a typical chemically amplified resist (CAR), the effect of these developers on stochastic defects were assessed. As a result, patterning investigations showed that the lithographic performance of the CAR developed in ETMAH is comparable to the those obtained with TMAH. In situ resist dissolution analysis using the high-speed atomic force microscope (HS-AFM) confirms this as it showed that the rate of CH formation during resist dissolution in both developers are relatively the same. Moreover, it was also understood that compared to the commonly used alkali developer concentration of 0.26N, a lower ETMAH developer concentration of 0.20N resulted in stochastic defect margin improvement, while maintaining lithographic performance. In situ resist dissolution analysis showed an obvious slowing down of CH pattern formation rate at 0.20N concentration, suggesting the possibility that of over-dissolution at the higher concentration condition, translating to an increase in merging CH defects. The results from this study show the advantages of further pursuing optimal developers for EUVL. This is especially significant as these findings indicate how optimal developers mitigate resist-based stochastic defects while maintaining lithographic performance.

Deep-learning-based SEM image denoiser Dorin Cerbu1, Sandip Halder1, Philippe Leray1 1IMEC, Kapeldreef 75, B-3001 Leuven, Belgium We report the development of a new method to denoise SEM images with the help of artificial neural networks. Upon using a preprocessing and training scheme tailored for SEM images of structures, most often encountered in semiconductor manufacturing, we can efficiently denoise images affected with varying degrees of noise severity and origin. In the figure below, we show an example of how we can use this filter efficiently to treat noisy images and improve the image quality. This can help in acquisition of more stable and better metrology data. Fig1(a) original image (b) Image which has been denoised using deep-learning based algorithms This development is of utmost importance for the case of post-litho processing step where resist nanostructures when SEM inspected are usually impacted by the electron beam and shrink, hence skewing critical dimension measurements. This is especially true as we push towards sub N-10 nm nodes. Application of our deep-learning processing scheme allows efficient noise reduction on SEM inspection images and helps us discern minor details previously shadowed by noise. This is extremely important as we move towards using EUV in high volume manufacturing. Small details can be crucial to understand the root-cause of stochastic and process defects. In previous work, we have already shown different approaches to understand stochastic defects [1-2]. The goal of this work is to enhance the image quality as much as possible to gain further fundamental understanding on nano-defects. [1] S. Halder et. al., ‘Using machine learning techniques to understand EUV stochastics, SPIE Photomask Technology + Extreme Ultraviolet Lithography, 2018 [2] K. Sah et.al., ‘EUV stochastic defect monitoring with advanced Broadband optical wafer inspection and e-Beam review systems’, SPIE Photomask Technology + Extreme Ultraviolet Lithography, 2018