Failure Analysis From Back Side of Die

Maintenance is a process carried out to maintain the reliability of individual/group assets. Positive displacement type pumps are commonly used in closed drainage systems as transfer pumps in oil and gas processing plants. However, there are times when the pump fails which requires further effort to prevent the failure from recurring. Efforts that can be made to overcome this are using the method of Analysis of the Root Failure (Root Cause Failure Analysis). The RCFA method uses recollection of evidence related to design, procurement, and operation of a tool to find root causes and latent causes of problems. As a result of gaps found between the design process, procurement which leads to the root cause of pump failure, this study recommends pump-operating companies to pay more attention to piping installation to support pump performance and coordination between owner, design, and procurement to prevent this failure from recurring.

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Fractography of Metals and Plastics

Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 μm across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

The switching power has been used in worldwide step by step. DC/DC converter is the core of a switching power. The research of reliability and failure analysis of the DC/DC converters is important to make products reliable and to maintain its performance under different loads. Based on the long-term experience of DC/DC converter failure analysis, two kinds of key failure modes of DC/DC converter which were component failure and assembly failure respectively were studied. In order to prevent the failure occurrence and ensure the reliability of DC/DC converter, several failure analysis case studies were given and the failure mechanisms and possible root causes of failure were investigated. Finally, several failure prevention methods were suggested.

This paper describes a new technique, called the Light-Induced State Transition (LIST) method that uses an optical beam induced current (OBIC) system for failure analysis of CMOS LSIs. This technique allows one to locate a low signal line short-circuited to a GND bus (or a high signal line short-circuited to a V/sub DD/ bus) in stand-by condition which is not possible with conventional failure analysis techniques such as photo-emission analysis, liquid crystal technique, or the conventional OBIC method. The effectiveness of the LIST method was verified by an experiment on inverter chains that included quasi-failures intentionally patched by FIB deposition. The LIST method has also been used for actual CMOS logic failure analysis, and has proved to be useful for finding a failure location rapidly.

Chapter 2 - Engineering failure analysis in chemical process industries

Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

Seven out of 12 pieces of hangers for superheater pipe were failed after one year in service. Failure analysis has been conducted to find out the root cause of failure. Hanger material is ASTM A182 Grade F22 Class 1. Fractography examinations revealed that the fracture mode is due to mechanical fatigue. Tensile test results show a tensile strength of 1015 MPa which is far beyond the minimum standard requirement of 415 MPa. The hardness of the failed hanger is between 270 to 325 HB, and un-failed hanger is around 245 HB, which are higher than the maximum standard requirement of 170 HB. The Charpy impact energy is 3 J, far below the standard requirement of 54 J. The microstructure in the bend area and the straight section contained tempered martensite and ferrite. Further examinations were conducted by heat treatment simulations to explore properties after heat treatment. Materials are subjected to full annealing treatment at 900°C, and normalizing at 955°C followed by tempering at 675°C. The average hardness is 154 HB after annealing, and 235 HB after normalizing and tempering. According to heat treatment simulation results, hanger material was supposed to be supplied under annealing condition where the hardness fulfils the standard requirement. Failure of superheater pipe hanger is due to improper heat treatment which promote brittleness and initiate premature crack during start-up. Crack initiation might also occur during post forging quenching. Fatigue crack propagation occur during service by small amplitude vibration.

Surface Mount Technology (SMT) ceramic capacitors are widely used on virtually every type of electronic product. In computer systems, SMT capacitors populate the majority of electronic parts found on each Printed Circuit Assembly (PCA) within the product, primarily as bypass or coupling devices between power and ground. As such, the opportunity for failure is substantially higher than with other commonly used active or passive components. Additionally, the relatively small ceramic bodies are prone to mechanical damage. Their proportionately high numbers, sensitivity to mechanical stress and difficulty in isolating to a specific failing device on the PCA (since many of these parts are in parallel with many other identical capacitors) all combine to make the successful isolation and analysis of the root cause of failure particularly difficult for the failure analyst. Often, the cause of failure is misdiagnosed, or the evidence is compromised by the methods used to perform the analysis. This paper will discuss the common failure mechanisms associated with SMT ceramic capacitors, as well as some innovative non-destructive isolation tools and techniques, including C-Mode Scanning Acoustic Microscopy (C-SAM), Infrared thermography (IR) and Micro-Focus X-ray analysis. Several case studies will be cited which demonstrate each of the mechanisms and methods. Additionally, the processes used to properly analyze these defects will be examined.

Leakage current study and relevant defect localization in integrated circuit failure analysis

Failure analysis of a reheater tube dissimilar metal weld failure in a 500 MW power plant

The influence of the charged back side on the transmission of highly charged ions through PC nanocapillaries

In this paper, an Intuitionistic Fuzzy TOPSIS model which is based on a score function is proposed for detecting the root cause of failure in an Offshore Boat engine, using groups of expert’s opinions. The study which has provided an alternative approach for failure mode identification and analysis in machines, addresses the machine component interaction failures which is a limitation in existing methods. The results from the study show that although early detection of failures in engines is quite difficult to identify due to the dependency of their systems from each other. However, with the Intuitionistic Fuzzy TOPSIS model which is based on an improved score function such faults/failures are easily detected using expert’s based opinions.

The optical beam induced current (OBIC) technique allows direct imaging of high voltage p-n junctions at a microscopic level under reverse operating conditions by measuring the local variation of the photocurrent. In this paper, we focus on demonstrating two essentially different applications of the OBIC technique: individual failure analysis and evaluation of device concepts by direct verification of the operation of the junction termination extension (JTE) as compared to simulation results.