Leakage current study and relevant defect localization in integrated circuit failure analysis

The authors provide an introduction to the operation of existing commercial atomic force microscopes (AFMs), present a variety of image data on integrated circuit related objects, and review reliability applications from examples. The AFM offers 3-D surface measurement capability from angstroms to over 100 mu m, the ability to image insulators directly without coating, and minimal sample preparation. These features indicate strong potential for applications in IC failure analysis and reliability, particularly as ICs move toward submicron geometries. Standard commercially available AFMs can create high quality images of a variety of semiconductor process related surfaces. The basic structure and dimensions as well as defects and contaminants can be easily seen. The resolution capability of the AFM will carry these abilities through any foreseeable reduction in geometry. Current AFMs are contact, ultra-low force devices that are limited to small sample sizes. Future developments will include non-contact AFMs and AFMs with the capability to accommodate complete wafers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Praise for Signal Integrity Effects in Custom IC and ASIC Designs For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. --Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip. --Kenneth L. Shepard, Professor, Columbia University book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity. --Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc. collection of papers...is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection. --Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley The editor has gathered together a collection of papers, both tutorial and advanced, that address a broad range of interconnect problems. --Jacob White, Professor, Massachusetts Institute of Technology Signal Integrity Effects in Custom IC and ASIC Designs compiles recent expert research papers in state-of-the-art IC (Integrated Circuits) design. It offers a detailed focus on all the major topics in understanding and modeling real-world IC signal integrity issues for CAD and IC design engineers, as well as graduate engineering students. Practical, in-depth discussion of interconnect effects, inductance effects, power grid and distribution noise, and substrate noise and coupling is included. This specialized coverage provides the knowledge necessary to overcome serious problems in new, more complicated IC designs, such as:Wired and wireless communications ICs Large custom analog mixed-signal ICs ASIC designs from 0.12 microns and above Integrated custom IC blocks in ASIC (Applications-Specific Integrated Circuit) designs

The switching power has been used in worldwide step by step. DC/DC converter is the core of a switching power. The research of reliability and failure analysis of the DC/DC converters is important to make products reliable and to maintain its performance under different loads. Based on the long-term experience of DC/DC converter failure analysis, two kinds of key failure modes of DC/DC converter which were component failure and assembly failure respectively were studied. In order to prevent the failure occurrence and ensure the reliability of DC/DC converter, several failure analysis case studies were given and the failure mechanisms and possible root causes of failure were investigated. Finally, several failure prevention methods were suggested.

Fractography of Metals and Plastics

This chapter discusses the application of scanning and transmission electron microscopy techniques, X-ray microscopy, as well as scanning probe microscopy for physical failure analysis. With the scaling-down of transistor features and interconnect dimensions and with the introduction of new processes and materials, physical failure analysis becomes more and more an essential task to exclude both yield-limiting process irregularities and reliabilityrelated failures in the semiconductor industry. Advanced imaging tools and techniques are needed to ensure high manufacturing yield and product reliability. Physical failure analysis is an essential task to exclude both yield-limiting process deviations and reliability-related failures in integrated circuit (IC) manufacturing industry. Its goal is to determine the root cause of failures or parameter deviations as a prerequisite for corrective actions. Polysilicon Gate Roughness, control of the transistor gate critical dimension with nanometer accuracy is a top priority task for leading-edge IC manufacturing.

The electronic components are the core of all electronic products, the reliability and maintainability directly affect manufacture products quality. And as products become more complex and more demanding. We need more reliable components. In order to solve this problem, we need to analysis how and why those components failed. Failure analysis cases are important data for analysis, data mining and improving reliability. China Electronic Product Reliability and Environment Testing Research Institute (CEPREI) is the earliest research organization engaged in reliability research and failure analysis in China, and has accumulated rich failure case data. By combining data mining methods such as Bayesian network, correlation analysis, we can perform statistical analysis and root cause analysis to assist failure analysis and improve product reliability. This paper will apply the failure analysis case of the electromagnetic relay, and explores and analyses related regular pattern.

With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

The typical electrical degradation on the complementary metal oxide semiconductor (CMOS) performance is due to defect in gate oxide layer. During integrated circuit (IC) infant mortality phase, stress tests introduced at wafer sort and final test in order to assured only good IC being deliver to end customer. Stress tests such as burn-in, gate stress, and quiescent current (IDDQ) test, demonstrated their competency to screen out this type of early failure. Nevertheless, the latent defect is a time dependent failure, which, affect the CMOS reliability after certain time, temperatures and application stress. Consequently, revise failure analysis technique has to be introduced in effective approach to compensate the problem in the current technology due to metal interconnection layers and dense for front side failure analysis (FA). The motivation of this work is to present the fault localization on the elevated IDD current of the faulty logic cells during the transition by photo localization technique and clarify gate oxide defect through circuit simulation. We have confirmed that the IDD scan test and photo localization technique were effective to localize faulty IC in silicon active area through front side.

Maintenance is a process carried out to maintain the reliability of individual/group assets. Positive displacement type pumps are commonly used in closed drainage systems as transfer pumps in oil and gas processing plants. However, there are times when the pump fails which requires further effort to prevent the failure from recurring. Efforts that can be made to overcome this are using the method of Analysis of the Root Failure (Root Cause Failure Analysis). The RCFA method uses recollection of evidence related to design, procurement, and operation of a tool to find root causes and latent causes of problems. As a result of gaps found between the design process, procurement which leads to the root cause of pump failure, this study recommends pump-operating companies to pay more attention to piping installation to support pump performance and coordination between owner, design, and procurement to prevent this failure from recurring.

Chapter 2 - Engineering failure analysis in chemical process industries

Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

Seven out of 12 pieces of hangers for superheater pipe were failed after one year in service. Failure analysis has been conducted to find out the root cause of failure. Hanger material is ASTM A182 Grade F22 Class 1. Fractography examinations revealed that the fracture mode is due to mechanical fatigue. Tensile test results show a tensile strength of 1015 MPa which is far beyond the minimum standard requirement of 415 MPa. The hardness of the failed hanger is between 270 to 325 HB, and un-failed hanger is around 245 HB, which are higher than the maximum standard requirement of 170 HB. The Charpy impact energy is 3 J, far below the standard requirement of 54 J. The microstructure in the bend area and the straight section contained tempered martensite and ferrite. Further examinations were conducted by heat treatment simulations to explore properties after heat treatment. Materials are subjected to full annealing treatment at 900°C, and normalizing at 955°C followed by tempering at 675°C. The average hardness is 154 HB after annealing, and 235 HB after normalizing and tempering. According to heat treatment simulation results, hanger material was supposed to be supplied under annealing condition where the hardness fulfils the standard requirement. Failure of superheater pipe hanger is due to improper heat treatment which promote brittleness and initiate premature crack during start-up. Crack initiation might also occur during post forging quenching. Fatigue crack propagation occur during service by small amplitude vibration.

The levelized cost of energy (LCOE) from PV systems can be reduced by maximizing the energy production of existing/future PV plants through increased availability. This can be achieved by detailed study of root cause and failure analysis of component failures leading to a systematic progress towards improving the reliability of various sub-systems. SunEdison owns/operates ~500 sites across the world and systematically collects field failure data in addition to power output and weather data. Analysis of this information allows following-up on corrective actions to eliminate/minimize the re-occurrence of failures and leads to continuous improvements. This paper will analyze some of the key findings from the system failures as follows: - Inverter failures not only cause most of the system outages, but also result in substantial energy losses. Component failures in PCBs and inverter software/firmware bugs are the most common root cause of system outages - From a systemic root cause perspective, lack of robust quality systems at multiple levels of the supply chain is quite evident, which points toward the need for collectively inculcating the quality culture at every stage of the supply chain - This paper will try to establish the need for "Continuous Improvement Process" (CIP) where systemic issues are confronted and solutions are internalized in the operating procedures as the only path to improving component reliability - For a given level of reliability, cost associated with servicing the plant becomes critical. This paper highlights the importance of using "cost of ownership" metrics for making procurement decisions

Failure analysis of a reheater tube dissimilar metal weld failure in a 500 MW power plant