Physical failure analysis in semiconductor industry – challenges to microscopy

As semiconductor manufacturing progresses to smaller process nodes, it is becoming increasingly difficult to climb the yield learning curve rapidly. The rate of yield learning dictates the growth and success of the semiconductor industry, and must be accelerated to fulfill competitive time-to-market, time-to-money and time-to-volume requirements. Software-based diagnosis plays a crucial role in yield learning. Diagnosis comprehends the test response of a failing circuit to determine the location, and sometimes, in addition, characterize the nature of a defect affecting the failing circuit. Besides identifying likely failure mechanisms and increasing the quality of chip testing, the feedback provided by diagnosis is used to select chips for physical failure analysis (PFA). PFA aims to visually examine a chip to characterize a defect, prevent similar defects in the future and, consequently, improve the design and manufacturing of a chip.However, PFA is often destructive, time- and cost-intensive, and not always successful. Diagnosis, on the other hand, is non-invasive and time- and cost-effective; moreover, it assists PFA and guides yield learning. The advantages of diagnosis, coupled with the diminishing performance of PFA with advancing technology, make it an encouraging facilitator for rapid yield learning.Therefore, the objective of diagnosis must be logic-level defect characterization to minimize (and ideally eliminate) the need for PFA, and accelerate yield learning. Logic characterization of a defect includes the derivation of its physical location and precise logic behavior. In this dissertation, a comprehensive diagnosis methodology is developed to actualize the aforementioned objective.The developed methodology comprises of three methods. LearnX/MD-LearnX is a physically-aware method that employs (a) the X-fault model to avert the elimination of a correct defect candidate and (b) machine learning to build a candidate-ranking model that learns the hidden correlations between the tester response and the defect candidates to pinpoint the correct candidate. PADLOC, which stands for Physically-Aware Defect LOcalization and Characterization, improves the physical location of a back-end defect (i.e., a defect that affects one or more interconnects and resides outside a standard cell) returned by LearnX/MD-LearnX by partitioning the defective net into physical subnets and identifying the subnets that influence defect excitation. In addition, PADLOC deduces the precise impact of a defect on the circuit functionality by examining its surrounding circuitry. NOIDA, which stands for NOise-resistant Intra-cell Diagnosis Approach, pinpoints the location of a defect within a failing standard cell implicated by LearnX/MD-LearnX. In contrast to prior work that typically constructs/employs a fault dictionary, NOIDA ascertains the location as well as the behavior of a front-end defect (i.e., a defect that resides inside a standard cell) by monitoring the logical activity of its intra-cell neighborhood. Additionally, NOIDA is resistant to circuit-level noise that may originate from potentially inaccurate transistor-level simulation. Results from numerous experiments reveal that our diagnosis methodology outperforms state-of-the-art commercial diagnosis. LearnX/MD-LearnX reports fewer defect candidates than commercial diagnosis for 69.4% silicon fail logs without losing accuracy. PADLOC implicates a smaller physical area for a defect for 47.2% silicon fail logs and attains at most 44X improvement. NOIDA reports an ideal diagnosis for 38.0% more front-end defects, when compared to leading-edge commercial diagnosis. In the presence of noise, NOIDA achieves an ideal diagnosis 7.6X more often.In summary, this dissertation endeavors to characterize a defect residing in a logic chip in terms of its precise physical location and logic behavior, which, consequently, most likely, enables rapid yield learning. The deployment of machine learning to pinpoint the correct candidate in LearnX/MD-LearnX, and the investigation of the neighborhood of a defect to determine its exact physical location and logic behavior in PADLOC and NOIDA are the novel components of this dissertation, and the reasons for its superiority over the state-of-the-art.

This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, density, cycle time, and technology issues of the hardware increase the difficulty of diagnosis. Since G5 first silicon, intense diagnostics and physical failure analysis (PFA) have successfully identified the root cause of many failures, including examples of process, design, and random manufacturing defects. This success is attributed to the three techniques described in this paper. For each technique, an example is presented to demonstrate its effectiveness.

As the device technology is progressing in the nanometer regime towards atomic scale, the famous comment “There is plenty of room at the bottom” by Richard Feynman about 60 years ago needs to be reviewed carefully and understood in detail. A recent comment “There is plenty of difficulty near the bottom” by device manufacturers depicts another face of the advancement in technology. The difficulty observed is in the path for building reliable devices. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to control the extension of even atomic level defects, especially when the dimensions are at nanometer level. At the early stages of technology development, the reliability estimation was through specific tests prediction to weed out defects. Many such tests are a routine and has helped to develop technology. However, at that time itself it was known that understanding device physics and solving the related problems at smaller dimensions are the key to success. As such, the device development at any technology level has been through the critical understanding of the failures through physical analysis and hence solving the issues. This procedure is the Building-in reliability in devices. It could be noted that many fundamental physics problems such as hot carriers, issues of dielectric breakdown and strength, electro migration and stress migration, electrostatic discharge issues, etc which paused the threat at different stages were solved fully or partially through physical failure analysis and understanding the related failure mechanisms. However, as the technology progressed with new materials at new dimensions, the problems also became more challenging. The tools which helped and being used for analysis itself have limitations due to the dimensional miniaturization. Moreover, the diversification in the manufacture from design to product through different vendors and stages invites a separate approach for building the product reliability. This tutorial discusses the fundamentals of reliability and failure analysis in its basic concepts and from where it can be understood using a physics based approach. The progression in devices from the conventional MOSFET and its dimensional shrinkage to nano scale MOSFET and then to new FinFET is discussed with a view to understand how the physical failure analysis can reveal the failure mechanisms to improve reliability. While evolving these processes to build reliability in nano scale devices, it is also understood that the fundamental problem remains the same as in early 1960s. That is where the “the plenty of room” is emerged as “plenty of difficulty”.

Physical failure analysis (PFA) is crucial to improving yield during the production life of an integrated circuit (IC). PFA begins with software-based diagnosis, which reports a set of likely failing candidates. A large set, which can result from test-set equivalent (TSE) faults, makes PFA success unlikely because each candidate may potentially have to be examined. Reducing the cardinality of a TSE fault class can reduce the time required for PFA since it likely decreases the number of candidates that must be examined. Additional (diagnostic) test vectors can be generated however to reduce class size. In this work, several layout-based physical metrics are defined and investigated for assessing the layout characteristics of a TSE fault class, which serves as an estimate of the time/difficulty required to perform PFA. In short, these metrics are used to define a physically-aware diagnostic resolution (PAR for short) for a fault class. A TSE fault class with a bad PAR likely requires more PFA effort than one with good PAR. To demonstrate the utility of PAR, a test-selection algorithm that chooses tests from an N-detect test pool based on the improvement in PAR is compared to techniques that use conventional definitions of diagnostic resolution. Comprehensive experiments reveal that fewer additional tests are needed when using PAR.

We usually do Physical Failure Analysis (PFA) to visualize the failure in the semiconductor process. First, we find the site-specific target (or failed cell). And then, we should do de-processing which contains lapping and chemical etch. As the semiconductor gets more complex and multi-layer, we should do multi-de-processing steps. If the failure has the oxide-material, we cannot know the cause of failure. Because the oxide can be removed by Hydrogen Fluoride (HF) chemical, which means the failure will be gone during de-processing step. We should use Focused Ion Beam (FIB) which can make a thin sample to exclude chemical step. High-resolution analytical tools such as Transmission Electron Microscopy (TEM) have become indispensable in PFA. We make a Dual-Axis TEM (DAT) method for PFA. We make a Plan-view TEM (PTEM) sample with FIB first, we can find an exact location of failure through the first step. And then, we make cross-sectional TEM (XTEM) sample with a site-specific target in PTEM sample. Below summarizes the four major steps and its precautions;1. Making a Planar lamella by FIB2. Observing a PTEM specimen with TEM(Precaution : zone axis should be adjusted exactly)3. Making a cross-section lamella by FIB(Precaution : Protection layer should be deposited on both sides)4. Observing a XTEM specimen with TEMWe propose DAT method to improve the problem of artifact in de-processing step. The TEM result with DAT method is shown in figure 4. We can know the exact location of failure with observing a PTEM sample. We can know the cause of failure with observing a XTEM sample. Moreover, we can analysis the chemical and physical information through DAT method. This method is very effective and has a high success rate in analysis. REFERENCE [1] A.E.M. De Veirman, “3-Dimensional’ TEM silicon-device analysis by combining plan-view and FIB sample preparation”, Materials Science and Engineering: B, 102(1-3), pp. 63-69, 2003. [2] Jon C. Lee, David Su, J.H. Chuang, “A Novel Application of the FIB Lift-out Technique for 3-D TEM Analysis”, Microelectronics Reliability Asset, 41(9-11), pp. 1551-1556, 2001. Figure 1

As the complexity of integrated circuits increases, the electrostatic discharge (ESD) protection devices become critical to reliability issues. However, the physical failure analysis of ESD devices is destructive and time-consuming. In this work, by using the X-ray microscopy (XRM), we study the abnormal change in the leakage current of diode-triggered silicon-controlled rectifiers (DTSCRs) ESD structure under transmission line pulsing stressing. XRM is nondestructive physical failure analysis method by showing the in-depth morphology information of the devices. The results show that the proposed ESD devices have two parts, one is the trigger diodes part and the other is the SCR part. The SCR part was severely damaged and the contact and vias are melted under the electrical stressing, while the trigger diodes part remains intact. The failure analysis is nondestructive, multi-view, and time-saving. It is enlightening the design of novel ESD devices.

The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

Thermal compression bonding is being widely used for fine pitch copper pillar assembly as it provides high die placement accuracy and bonding suitable for mass production. In the current work, chip package interaction induced ILD integrity failures under thermo-compression assembly induced stresses were investigated. A step by step EFA (Electrical Failure Analysis) plus PFA (Physical Failure Analysis) methodology was developed to isolate the failing location and confirm the fail mode. The key steps include initially dataloging the fails and running the data through ATPG (Automatic Test Pattern Generation) tools to localize the failing nets. The PFA was then focused on the ILD sections in the vicinity of the Cu pillar interconnect (as the pillar is the primary load transference link between the die and substrate). Specific fail modes were then identified using a combination of Scanning Optical Microscopy (SOM), Scanning Acoustic Microscopy (SAM), layer by layer de-processing and Focused Ion Beam (FIB) cross-sections. The paper summarizes the key findings, failure modes from the study — it was found that the assembly process could result in damage initiation in the ILD which results in functional failures during subsequent reliability testing. The scale of induced damage makes it nearly impossible to detect using either traditional eFA, PFA or a combination of the two. Additionally, key assembly and design parameters, to resolve the fails are also discussed.

In this poster, we share our industrial experiences on running chain diagnosis and PFA (Physical Failure Analysis) on a wafer that suffered from low yield. In addition, case study on PFA will be illustrated.

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Three major cause of failure had been established for bushings with over 20 years of service namely: seals damaged, leaks at expansion gas chamber and corrosion at bushing tap. In the paper, each root cause of failure is illustrated with true faults occurred while in service. Then detailed analysis is presented, and more important, some corrective measures to prevent bushing explosion had been established. Those include inspection procedures that had been applied to identify and remove from service damaged bushings. Furthermore, those bushings had been disassembled and investigated at bushing repair facilities. Internal inspection confirmed suspected damaged and promote corrective maintenance actions. Results demonstrate that paper insulation is largely unaffected by these root causes if treated at early stages. Most important, the dielectric strength of the main insulation is restored after vacuum treatment and impregnation with new oil. Bushing reliability had been evaluated in laboratory condition with impulse, AC overvoltage and partial discharge measurements, demonstrating that it is possible to restore reliability on aged bushings, if the three main cause of failure are corrected on time.

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

Microscopic imaging and characterization of semiconductor devices and material properties often begin with a sample preparation step. A variety of sample preparation methods such as mechanical lapping and broad ion beam (BIB) milling have been widely used in physical failure analysis (FPA) workflows, allowing internal defects to be analyzed with high-resolution scanning electron microscopy (SEM). However, these traditional methods become less effective for more complicated semiconductor devices, because the cross-sectioning accuracy and reliability do not satisfy the need to inspect nanometer scale structures. Recent trends on multi-chip stacking and heterogenous integration exacerbate the ineffectiveness. Additionally, the surface prepared by these methods are not sufficient for high-resolution imaging, often resulting in distorted sample information. In this work, we report a novel correlative workflow to improve the cross-sectioning accuracy and generate distortion-free surface for SEM analysis. Several semiconductor samples were imaged with 3D X-ray microscopy (XRM) in a non-destructive manner, yielding volumetric data for users to visualize and navigate at submicron accuracy in three dimensions. With the XRM data to serve as 3D maps of true package structures, the possibility to miss or destroy the fault regions is largely eliminated in PFA workflows. In addition to the correlative workflow, we will also demonstrate a proprietary micromachining process which is capable of preparing deformation-free surfaces for SEM analysis.

This paper describes the integrated fast failure analysis/yield enhancement system used at Motorola's MOS-12 fab, established with the goal of providing high speed diagnostics and feedback. This goal was achieved through tight integration of in-fab inspection tools with electrical test equipment, out-of-fab analytical tools, and software tools. At this facility, the use of common file formats permits data exchange between wafer inspection tools, optical review stations, SEM, FIB, and electrical work bench testers. Wafer images generated at all diagnostic tools are stored on a video archival/retrieval system (VARS<SUP>TM</SUP>). Correlation is a powerful tool for reducing failure analysis time and increasing failure analysis efficiency. By overlaying in-line inspection data with process, parametric, sort bin, and bitmap data, the locations of potential killer defects are rapidly identified. Physical failure analysis is performed on selected correlated failures to confirm the cause of device failures. Using analytical instruments with full wafer capability, in-line inspection or bitmap information are used to quickly locate the defects of interest. This approach has been successfully used to significantly reduce FA time compared with traditional FA methods. Fast failure analysis/yield enhancement is demonstrated with three case studies.

It has been long recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach using memory bitmapping. However, the success rate of defect detection, especially for soft single-column failures, which is one of the most complex failure modes of an SRAM failure, is decreasing when using traditional physical failure analysis (PFA) with only the bitmap available for guidance due to a variety of invisible or undetectable defects that cause a leakage behavior in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, conductive atomic force microscope (C-AFM) [1-5] is introduced to perform junction-level fault isolation prior to attempting PFA. In this study, the quantified data extracted using the C-AFM can also be used to establish a connection between the failure mechanism discovered and the soft single column failure mode.