Fast BIST Mechanism for Faster Validation of Memory Array

Area Overhead and Power Analysis of March Algorithms for Memory BIST

Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.

Integrated circuit (IC) applications have become viable, reliable, and cheaper with deep-submicron technologies in VLSI industry. SoC (system on chip) is a microchip, which holds the necessary hardware and software to implement various functions onto a single chip. An IC should be tested during design process to check the correctness of the design and also to check the functionality of the design after fabrication. Testing cost shares almost half of the manufacturing expenditure. Achieving high-test quality in reduced VLSI geometry increases the complexity of the testing methods because of huge volume of test data. Automatic testing equipment (ATE) reduces testing efforts, but it has limited memory in comparison with the huge volume of the test data. One of the methods to reduce the burden of ATE is test data compression. The advantages of test data compression are as follows: (i) reduction in memory requirement for ATE and (ii) reduction in testing time. Though many advanced algorithms are used for testing of VLSI circuits, most of them are expensive in terms of test data volume and power. This survey discusses all the test data compression methods, and it helps the researchers in testing domain.

This paper is about a generic method for designing shared memory BIST systems. In order to be of practical use, such a method should work with whatever memory kinds and BIST components are available for the technology used. It should accept arbitrary sharing rules for grouping memories under a wrapper, and it should take individual values of BIST component area, memory test time and memory testing peak power as parameters. We present such a method that uses genetic algorithms for its optimization phase, together with its industrial implementation, and numerical evidence for the value of the method. It is integrated into STMicroelectronics' BIST definition flow.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

In the modern System on Chip (SoC)-based designs, embedded memory occupies the majority of the area. Therefore, the demand for fast self-testing plays a vital role in the SoC device as its memory density increases. The focus of this research study is to provide a self-testing mechanism integrated with the SoC design for fault diagnosis and failure analysis. In particular, this paper proposes a controller design to test memories at SoC devices, called a memory built-in self-test (MBIST) controller. This controller works on the principle of the proposed March-ee (enhanced elements) algorithm with the primary objective to improve the test speed, fault coverage, and power consumption at a low area overhead. The complete design of the MBIST controller with the associated March-ee algorithm is minimal and easy to be integrated into any SoC device to provide a vibrant feature of memory fault detection. The results obtained are compared with that provided by the existing March algorithms, using the same design specifications, where the proposed March-ee MBIST controller has shown better results in terms of power consumption, fault coverage, timing, and area.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

Intellectual property (IP) cores reused technology improves system-on-a-chip (SoC) design productivity. However, with more IP cores embedded in the deeper levels, the hierarchical architecture of SoC becomes complex, which also makes the test difficult. A scan chains combined-balance (SCCB) strategy is proposed in this paper to reconfigure and balance the scan chains, which helps reduce test time and overhead. The SCCB strategy is different from the traditional test method, wherein the test access mechanism (TAM) and Scheduling are established as a virtual flattened form. We take experiments to verify the SCCB strategy based on the ITC'02 benchmarks. The experimental results show that the SCCB strategy is effective.

Modem VLSI circuits with extensive built-in self-test (BIST) resources have the problem of long testing time if the testing for the different parts of the circuits are executed successively. Herein, we present a heuristic solution, called Weighted Cluster Partitioning (WCP), to the problem of long testing time for VLSI circuits. Some of the techniques in current use exploit parallelism in testing VLSI circuits, but the computation is quite expensive. Our solution is a more efficient and effective procedure which explores the space of concurrent test schedule and leads to a considerable reduction of testing time by suitable incorporation of BIST in the circuit.

There are practical, clinical circumstances in which a decrease in test time for evoked otoacoustic emissions would be of economic or practical value. In addition, there are circumstances in which it is desirable to obtain more diagnostic information from the evoked emission. This preliminary report concerns predominantly one of these aspects but considers both of them. It is not possible to reduce the test time by simply increasing the stimulation rate because responses and stimuli will overlap and give rise to contaminated responses. However, these limitations can be overcome if a maximum length sequence of clicks is used. These sequences of clicks and silences enable responses of a duration greater than the time between stimuli to be recorded and deconvolved to produce an uncontaminated response. Conventional recordings at stimulus rates of 33/s and 50/s have been taken together with maximum length sequence recordings at rates up to 840/s and the waveforms correlate very well. Although the emission shows some adaptation at the highest stimulation rate this does not prevent a significant reduction in test time.

Single-photon emission computed tomography is a tomographic imaging method that acquires a projection image by rotating a gamma camera around by 380° or 180°. For myocardial single-photon emission computed tomography, 180° acquisition is common, but it has limitations including an incomplete reconstruction, which can distort the resulting image. It is possible to produce a complete reconstruction using 360° acquisition, but the testing time is long and is burdensome to patients. The nonuniform sampling pitch acquisition (NUSPA) method devised in this study involves reducing the total sampling count using NUSPA that reduces the sampling pitch in the range in which the gamma cameras are closer to the myocardium (RAO45-LPO45) and increases it elsewhere. The NUSPA-1 method based on a 6° sampling pitch had 20 views fewer than 360° acquisition. In addition, the NUSPA-2 method based on a 3.75° sampling pitch had 60 views fewer than 360° acquisition, considerably reducing the testing time. The acquired sinograms from the NUSPA methods were subjected to nonuniform rational B-spline surface interpolation processing, producing data with a uniform sampling pitch, after which image reconstruction was performed. The images after nonuniform rational B-spline interpolation for both the line sources and heart-liver phantom investigated in this study were not found to have the distortion observed from 180° acquisition or a count decrease at the center, resulting in image quality nearly equivalent to 360° acquisition. This method enabled a reduction in testing time without impacting image quality.

This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low-level simulation models. Traditionally, alternate test makes use of circuit and process-level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a "gray-box" approach by creating a high-level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front-end chip, for which 13 specifications including S-parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy

To perform a clinical comparison of the Humphrey Full Threshold strategy with its intended replacement, SITA Standard, regarding testing time, reproducibility, and measured threshold sensitivity in normal subjects and glaucoma patients. Thirty-eight healthy volunteers and 80 patients with primary open-angel glaucoma underwent central 30-2 testing with both Full Threshold and SITA strategies using a Humphrey HFA 2 Model 740 perimeter. The testing time, reproducibility, and measured threshold sensitivity of the two strategies were compared. The testing time for measurements with SITA was 56% lower in normal subjects and 45% lower in glaucoma patients than with Full Threshold. Cases having higher mean sensitivity or cases requiring longer testing time for Full Threshold had a greater percentage reduction in testing time for SITA. The test-retest variability studied in normal subjects was lower, but not significantly so, with SITA (2.9%) than with Full Threshold (3.4%). The mean sensitivities of SITA were higher (1 dB) than those of Full Threshold not only in normal subjects but also in glaucoma patients. This higher sensitivity in SITA was found irrespective of the order of the two tests both in normal subjects and glaucoma patients. Analysis by each testing point revealed that the difference was not dependent on the test point position or the sensitivity at the point. SITA has greater patient acceptability than the Full Threshold strategy. However, the difference in sensitivity can be considerable in a serial comparison of one patient's fields tested by Full Threshold and SITA.