Fast cache simulation for host-compiled simulation of embedded software

Increasing the speed of cache simulation to obtain hit/miss rates enables performance estimation, cache exploration for embedded systems and energy estimation. Previously, such simulations, particularly exact approaches, have been exclusively for caches which utilize the least recently used (LRU) replacement policy. In this paper, we propose a new, fast and exact cache simulation method for the First In First Out(FIFO) replacement policy. This method, called DEW, is able to simulate multiple level 1 cache configurations (different set sizes, associativities, and block sizes) with FIFO replacement policy. DEW utilizes a binomial tree based representation of cache configurations and a novel searching method to speed up simulation over single cache simulators like Dinero IV. Depending on different cache block sizes and benchmark applications, DEW operates around 8 to 40 times faster than Dinero IV. Dinero IV compares 2.17 to 19.42 times more cache ways than DEW to determine accurate miss rates.

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

Modular Multilevel Converter (MMC) is a mainstream technology in the field of flexible DC transmission engineering. The establishment of electromagnetic transient simulation model of MMC is the basis for theoretical research and engineering application. The Thévenin’s equivalent-based electromagnetic transient model of MMC has high simulation accuracy and less simulation time, which is widely used in the simulation system of MMC with high level number. However, the model is difficult to simulate the internal electromagnetic transient process of the submodule, such as the inability to effectively measure the current stress of the IGBT and the continuity diode when testing and analyzing the equivalent experimental stress, as well as the inability to simulate and analyze the internal faults of the submodule. In order to solve this problem, this paper proposes a highly accurate and efficient electromagnetic transient simulation model of MMC converter based on PSCAD/EMTDC. Specifically, the internal sub-modules of the MMC model are divided into two categories: special sub-modules and general sub-modules. For the special sub-modules, the detailed models are established respectively; for the general sub-modules, the Thévenin’s equivalent model is established. The model has high simulation speed and accuracy, while the interface is generalized and preserves the station-level and valve-level control strategies. The simulation is carried out by PSCAD/ EMTDC, and the experimental results verify the correctness and effectiveness of the proposed modeling method.

A modelling platform which can provide accurate measurement for delay with fast simulation speed is in high demand for embedded system design. Quick Emulator (QEMU) is an open source emulator capable of performing full system emulation without the need of having access to real target hardware. QEMU doesn’t emulate cache. Presence of cache significantly affects the memory latency. Hence, integrating cache is important to get approximate performance parameters for an instruction set simulator.In this study, Pycachesim (cache simulator) has been integrated with QEMU 6.1. Using this the instruction cache has been implemented. Our system has been tested by booting Linux OS and executing free Real Time OS (RTOS) based periodic application on ARM architecture. Our implementation can simulate multiple cache levels with different cache configurations giving an accurate number for stores, loads, hits and misses.

Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.It should be observed that some of the above goals are in mutual conflict. For example, modeling ease and high execution speed are normally only achievable by a sacrifice in accuracy, and high accuracy is only possible by more elaborate modeling efforts or slower execution speeds, or both. As a consequence it becomes important to achieve a balance between these goals. The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method.A new logic and fault simulator, VOTE (Verification of Test Effectiveness) is described. The specifics to be described here fall into two categories: those which are of general interest, and those which are strictly implementation items.

Accuracy of high resolution coastal flow speed simulations during and outside of wind, wave and stratification events (Gulf of Lion, NW Mediterranean)

The paper proposes an adaptive model reduction approach based on tensor decomposition to speed up time-domain power system simulation. Taylor series expansion of a power system dynamic model is calculated around multiple equilibria corresponding to different load levels. The terms of Taylor expansion are converted to the tensor format and reduced into smaller-size matrices with the help of tensor decomposition. The approach adaptively changes the complexity of a power system model based on the size of a disturbance to maintain the compromise between high simulation speed and high accuracy of the reduced model. The proposed approach is compared with a traditional linear model reduction approach on the 140-bus 48machine Northeast Power Coordinating Council system.

In traditional agent-based simulation system, the number of agents and simulation time are not critical issues, because the systems perform with only small part of the data. However, the number of agents and simulation speed are important factors in large-scale agent-based simulation and high speed simulation domain. In this paper, we describe design issues of the large- scale agent-based simulation framework for demographic and welfare. Keyword: Agent based modeling, large-scale simulation, demographic simulation, simulation framework 1 Background An agent-based micro-simulation(ABMS; Agent Based Modeling / Simulation) has emerged as the future technology for analysis and prediction of economic and social phenomena. So many countries have involved in the development of the technology. FuturICT, the EU's FET (Future and Emerging Technologies)(1), is a flagship pilot project for a sustainable future society in terms of large-scale data analysis and forecasting techniques, and OECD countries have an effort to obtain a population simulate the system reflecting their social/economic/cultural characteristics. Especially, several countries, United States, Canada, Sweden, the United Kingdom, Australia, already have simulators capable of processing hundreds of thousands of agents. Due to the development of Distributed parallel computing technology and large- scale data obtained, Effective policy formulation and implementation based on data can be available and be expected to the0.5%productivity growthper year in the public administration sector. (2) This paper describes design considerations and implementation issues for constructing a Large-scale Agent-based Demographic Micro-simulation Framework. In traditional agent-based micro-simulator, numbers of agents of target model do not exceed several hundreds of thousands. In case of NetLogo, the simulation speed of a target model become slow down significantly when numbers of agents of the model exceed ten thousand. This paper describes design considerations and implementation issues for constructing a simulation framework that will be adopted to develop a large-scale agent-based demographic micro-simulation system for Korea.

Reconfigurable Processor (RP) provides great flexibility of hardware re-configurability through software solution for high-performance computing. RP is used as a DSP in Samsung DTV and Camera to run the Audio, Video codecs and image quality enhancement algorithms. RP runs in two modes: VLIW (Very Large Instruction Word) and CGRA (Coarse Grain Reconfigurable Array). To minimize the time-to-market of products, application developers of the RP require a fast and cycle-accurate profiling-enabled simulator to verify the functionality of applications and to optimize the hot-spots (performance critical codes). Further, fast simulation is necessary to verify the functionalities for certification of various standards of multimedia (DivX, Dolby, etc.). The state-of-the-art RP simulators are very slow running at 2 MIPS (Million instructions per second) in CGRA mode and 4 MIPS in VLIW mode, running on x86 host processor at 3.4 GHz. We propose FastSim, a fast compile based cycle-accurate simulator for RP, which yields simulation speed of 900 MIPS in CGRA mode and 1600 MIPS in VLIW mode with > 99.5% core cycle accuracy. Thus, FastSim enables ∼400x faster simulation when compared to existing RP simulators. FastSim in VLIW mode is 2x faster when compared to the state-of-the-art functional simulators, and 16x faster when compared to cycle-accurate simulators, of the VLIW and RISC processors in the industry. FastSim speed is also comparable to application running time on native x86. The faster simulation speed is achieved with the use of an innovative maximal static analysis in both VLIW and CGRA modes.

Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip area. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in design space exploration, especially when there are hundreds of design points and the traces are huge. In this article, we propose a novel analytical approach for design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, we first model the cache states at each point of the CFG in a probabilistic manner. Then, we exploit the structural similarities among related cache configurations to estimate the cache hit rates for multiple cache configurations in one pass. Experimental results indicate that our analysis is 28--2,500 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.2% average error) in estimating cache hit rates for a large set of popular benchmarks. Moreover, compared to a state-of-the-art cache design space exploration technique, our approach achieves 304--8,086 times speedup and saves up to 62% (average 7%) energy for the evaluated benchmarks.

The complexity of multi-level cache hierarchies simulation is much more complicated than that of single-level cache simulation, so that it is highly desirable to develop some efficient simulation methods for multi-level cache hierarchies performance analysis. A one pass multi-level unified cache hierarchies simulation method is developed based on stack model and inclusion properties. Recently, many processors utilized split instruction and data caches in the first cache level. A one pass multi-level hybrid cache simulation method is proposed for more generalized hierarchies. These two one pass simulation methods have been implemented. The simulation results show the effectiveness of these two one pass simulation methods. >

Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to improve the performance of ISSes. A prevalent technique is compiled simulation, which translates target programs into host instructions. But orders of magnitude of speed deterioration is inevitable since the difference between target and host Instruction Set Architectures (ISAs) can be large. An alternative is to emulate the program without sticking to binary compatibility. The performance problem is solved by using native execution. However, these emulators either require a special programming language, or a given Application Programming Interface (API). Last but not least, it is not trivial to integrate an emulator into a system simulator (which provides devices, external memory, etc., that the embedded programmers do care). In this paper, we propose a fast and generic hybrid simulation approach using virtualization technique to accelerate simulation and simulator-based debugging of C programs. A novel virtual coprocessor (VCP) is introduced as a processing element which executes C functions at high speed. This approach is C89 compliant and compatible with third party libraries and platform dependent code. It is also retargetable and can be integrated with existing ISSes. Two different ISAs are supported at present: MIPS and mAgic DSP. The average execution speed of the coprocessor is about 100 million simulated instructions per second.

SPICE type simulation using compact models is a very useful tool for predicting circuit performance under ESD stress conditions. However device models valid in the ESD current/voltage operating region are not widely available. This paper starts with a brief description of compact modeling for ESD devices working in snapback mode. A practical macro modeling approach for modeling snapback of MOS and LVSCR is then introduced. It uses advanced industry standard BJT and MOS models. This method's advantages are simplicity, high simulation speed, wider availability, and reduced convergence issues

The development of electric vehicles (EV) necessitates the search for new solutions for configuring powertrain systems to increase reliability and efficiency. The modularity of power supplies, converters, and electrical machines is one such solution. Among modular electric machines, dual three-phase (DTP) motors are the most common in high-power drives. To simplify low and medium power drives for EVs based on DTP PM motor, it is proposed to use a BLDC drive and machine of the simplest design – with concentrated windings and surface mounted PMs on the rotor. To study and create such drives, an improved mathematical model of DTP PM machine was developed in this work. It is based on the results of 2D FEM modeling of the magnetic field. According to the developed method, the dependences of the self and mutual inductances between all phase windings from the angle of rotor position and loads of different motor modulus were determined. Based on these inductances, the circuit computer model of DTP PM machine was created in the Matlab/Simulink. It has a high simulation speed and a high level of adequacy, which is confirmed by experimental studies with a mock-up sample of the electric drive system.

Benchmarks capture the essence of many important real-world applications and allow performance, and power analysis while developing new systems. Synthetic benchmarks are a miniaturized form of benchmarks that allow high simulation speeds and act as proxies to proprietary applications. Software architecture principles guide the development of new applications and benchmarks. We leverage software architectural patterns in developing synthetic benchmarks for embedded multicore systems. We developed an automated framework complete with characterization and synthesis components and performed experiments on PARSEC and Rodinia benchmarks. Our benchmarks can be run on any given infrastructure, that is, SMP or message passing, unlike previously developed benchmarks. Hence, this allows us to target heterogeneous embedded multicore systems. Our results show that the synthetic benchmarks and the real applications are similar with respect to various micro-architecture dependent as well as independent metrics.