Using software architectural patterns for synthetic embedded multicore benchmark development

Software architecture involves a series of decisions based on many factors in a wide range of software development. Architects face recurring issues in different software architecture design, and to reduce huge cost and risks, software architecture decisions can rely on a set of idiomatic patterns commonly named architectural styles or patterns. Architectural pattern determines the vocabulary of components and connectors that are used in instances of the pattern together with a set of constraints to combine the two. Little contemporary data exists to document actual practices used by software professionals when selecting and incorporating architectural patterns for their projects in industry. Therefore, a comprehensive survey of software professionals was conducted to attempt to discover these practices. This exploratory survey and its quantitative results offer opportunities for further interpretation and comparison. Data from this survey are presented in this paper and include characteristics of projects, practices, organizations, and practitioners related to the usage of architectural patterns. Some of the notable findings include that architectural patterns are widely used in software projects with the Model–View–Controller being the most common. Despite reported difficulties in incorporating architectural patterns, the majority of the software professionals revealed that patterns were the most essential for completing the projects. The most difficult pattern to implement and the most expensive to adopt was the peer-to-peer, while the easiest was the client–server.

The Internet of Things-based systems and software allow computations anywhere at any time by interconnecting individuals, networks, services, computers and artefacts that allow autonomous systems to form digitized communities. As the blueprint for software-intensive applications, and software architecture that precise the complexity of a network’s planning, development, and changing phases to effectively and efficiently build complex IoT-driven applications. In any case, there exists no comprehensive analysis in the state of the research on the adoption of MSA for IoT systems. This study effort is needed to explore architectural concepts and practices for designing and developing IoT software to excel state-of-the-art for IoTs along with suggestions and recommendations for IoT software to the adoption of MSA to fulfil the identified gaps. A systematic analysis was coordinated, covering up the literature on existing IoT solutions by studying 140 qualitatively selected articles performed between 2005 and Jan 2020. One hundred forty articles were comprised in this SLR. The findings of this study demonstrated different research topics including software architectural styles, patterns, and models to build IoT software. This research presents cloud-based computing environments, autonomous, software-defined networking, and responsive applications, and IoT-driven agent-based systems, (1) thirteen MSA architectural and design patterns for IoTs and classification of patterns, (2) classification of software architectures for IoTs into nine main categories and their sub-categories, (3) twenty-three most investigated IoT challenges, and (4) mapping of IoT challenges with software architectural solutions. The study revealed the innovative work on IoT software architecture and trends that help in the creation and dynamic adaptation of IoT software for reusability, automation and human decision-making. The outputs of this SLR are useful in revealing many recommendations to the software industry, software engineering community, and computer sciences community with over the past 15 years of research into the adoption of MSA. This study reflects a distilled awareness of architectural practices and principles to assist researchers and practitioners in promoting information sharing software architectural roles and responsibilities for the Internet of Things software.

A review is presented on the currently available technologies for nuclear reactor analyses by computer. The important distinction is made between traditional computer calculation and advanced computer simulation. Simulation needs are defined to support the design, operation, maintenance and safety of isotope production reactors. Existing methods of computer analyses are categorized in accordance with the type of computer involved in their execution: micro, mini, mainframe and supercomputers. Both general and special-purpose computers are discussed. Major computer codes are described, with regard for their use in analyzing isotope production reactors. It has been determined in this review that conventional systems codes (TRAC, RELAP5, RETRAN, etc.) cannot meet four essential conditions for viable reactor simulation: simulation fidelity, on-line interactive operation with convenient graphics, high simulation speed, and at low cost. These conditions can be met by special-purpose computers (such as the AD100 of ADI), which are specifically designed for high-speed simulation of complex systems. The greatest shortcoming of existing systems codes (TRAC, RELAP5) is their mismatch between very high computational efforts and low simulation fidelity. The drift flux formulation (HIPA) is the viable alternative to the complicated two-fluid model. No existing computer code has the capability of accommodating all important processes in the core geometry of isotope production reactors. Experiments are needed (heat transfer measurements) to provide necessary correlations. It is important for the nuclear community, both in government, industry and universities, to begin to take advantage of modern simulation technologies and equipment. 41 refs.

System-on-Chip (SoC) platforms, being a part of contemporary embedded and multicore systems, must be complemented by strong behavioural modeling to verify, validate, and debug them. This work proposes AutoModel ML, a novel machine learning-assisted method that learns high-level behavioural models directly from SoC execution traces. Our pipeline, which combines recurrent neural networks with causality analysis based on constraints, constructs annotated causality graphs initially. They are converted into symbolic constraints and solved by SAT/SMT in an attempt to achieve compact finite state abstractions, like methods such as AutoModel. Empirical evaluation on synthetic benchmarks and real-world multi core SoC workloads (via gem5) demonstrates some significant enhancements: automated causality discovery among messages, recovering over 90% of known protocol traces; ML-augmented abstraction synthesis with a fidelity-explainability tradeoff; counterexample-guided iterative refinement with ~30% improvement in model completeness; and real-world application in protocol verification, anomaly detection, and hardware debugging. Our results indicate that AutoModel ML not only improves upon conventional trace mining methods in terms of scalability and precision, but also generates explainable models with the ability to generalize beyond seen executions. Through the significant diminishment of the amount of manual model engineering required, this system makes scalable, automated SoC behavioral modeling an attainable goal, a step toward cognitive, ML-driven hardware verification.

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of systems-on-chip (SoC). These models are written in C++ primarily because it is possible to achieve very high simulation speeds, but also because it is productive to code at high levels of abstraction. In this paper we present a modeling methodology that continues to exploit the inherent advantages of writing models in C++ while ensuring that they are usable for formal verification of RTL through the use of sequential equivalence checking technology. An industrial case study is presented to show the validity of the approach.

In this chapter, a cycle approximate simulator for multi-processor system-on chip is presented. The aim of this simulation tool is to enable an enhanced software/hardware analysis capability for bus based systems. The most important contributions are represented by its high flexibility (easy configuration of a SoC using dedicated libraries for generic and specific components and easy integration of other simulators and models), accurate modeling of features specific to multiprocessor systems (busses, inter processor communication mechanisms, etc), accurate implementation of a wide range of performance metrics and power consumption estimates (for processors that support this) and high simulation speed. This way, the proposed simulator can be used for both hardware architecture design exploration and software development.

Surrogate algorithms such as Bayesian optimisation are especially designed for black-box optimisation problems with expensive objectives, such as hyperparameter tuning or simulation-based optimisation. In the literature, these algorithms are usually evaluated with synthetic benchmarks which are well established but have no expensive objective, and only on one or two real-life applications which vary wildly between papers. There is a clear lack of standardisation when it comes to benchmarking surrogate algorithms on real-life, expensive, black-box objective functions. This makes it very difficult to draw conclusions on the effect of algorithmic contributions and to give substantial advice on which method to use when. A new benchmark library, EXPObench, provides first steps towards such a standardisation. The library is used to provide an extensive comparison of six different surrogate algorithms on four expensive optimisation problems from different real-life applications. This has led to new insights regarding the relative importance of exploration, the evaluation time of the objective, and the used model. We also provide rules of thumb for which surrogate algorithm to use in which situation. A further contribution is that we make the algorithms and benchmark problem instances publicly available, contributing to more uniform analysis of surrogate algorithms. Most importantly, we include the results of the six algorithms on all evaluated problem instances. This unique new dataset lowers the bar for researching new methods as the number of expensive evaluations required for comparison and for the creation of new surrogate models is significantly reduced.

There is a plethora of models, techniques and tools that support model-and component-based software development of vehicular distributed embedded systems. However, a large majority of them have a limited or no support to model and specify end-to-end resource reservations on the software architectures of these systems. Resource reservations allow flexibility during the development and execution of such complex systems without jeopardizing their predictable behavior. As a result, several applications in the system that share the same hardware platform can be developed independently. In this paper we identify several requirements that any existing component model should fulfill in order to support the modeling of end-to-end resource reservations on the software architectures of such systems. As a proof of concept, we extend the Rubus Component Model (RCM) by fulfilling these requirements. RCM is used for the development of control functionality in vehicular embedded systems by several international companies. We also provide a technique to extract execution models from the software architectures of these systems with resource reservations. In order to show the usability of our technique, we model a vehicular distributed embedded system with the extended component model and extract the execution model from the software architecture augmented with end-to-end resource reservations.

This paper presents a new parallelization model, called coarse-grained thread pipelining, for exploiting speculative coarse-grained parallelism from general-purpose application programs in shared-memory multiprocessor systems. This parallelization model, which is based on the fine-grained thread pipelining model proposed for the superthreaded architecture, allows concurrent execution of loop iterations in a pipelined fashion with runtime data-dependence checking and control speculation. The speculative execution combined with the runtime dependence checking allows the parallelization of a variety of program constructs that cannot be parallelized with existing runtime parallelization algorithms. The pipelined execution of loop iterations in this new technique results in lower parallelization overhead than in other existing techniques. We evaluated the performance of this new model using some real applications and a synthetic benchmark. These experiments show that programs with a sufficiently large grain size compared to the parallelization overhead obtain significant speedup using this model. The results from the synthetic benchmark provide a means for estimating the performance that can be obtained from application programs that will be parallelized with this model. The library routines developed for this thread pipelining model are also useful for evaluating the correctness of the codes generated by the superthreaded compiler and in debugging and verifying the simulator for the superthreaded processor.

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. Methods in the first group (e.g., software instrumentation), can be accurate but have unacceptable overheads and offer no insight into the interaction of the software and the hardware. Methods in the second group (e.g., hardware supported) run in real time and connect code to the response in the architecture, at a considerable decrease in accuracy, with a high degree of specificity to the hardware and therefore with limited actionable information made available. In this work, we focus on the latter group - the collection and analysis of raw performance data sourced from hardware Performance Monitoring Units, built into the majority of processors. The periodic collection of samples (Event Based Sampling), containing code locations, for instance, can be triggered on events such as retired instructions or cache misses. We quantify accuracy improvements to existing methods, propose a better performing method of performance data collection and a new architecture-agnostic method of performance data analysis. In our experiments, we analyze compiled, large-scale production workloads, industry standard benchmarks, and micro-benchmarks reproducing specific architectural behaviors. First, we focus on performance data collection methods and their accuracy, when establishing instruction retirement rates. These vary from least to most advanced and we examine the low level factors influencing accuracy. In particular, we employ a method based on Last Branch Records, a hardware facility present on some Intel architectures, which allows for the sampling of short records of last taken branches leading up to the sample. We compare the most commonly used method, its improved derivatives and the Last Branch Record based method. With respect to the first method, we observe accuracy improvements of up to 18x on synthetic benchmarks and 15x on real applications. Second, to further improve accuracy, we propose a new collection method named Hybrid Basic Block Profiling, fusing those based on Last Branch Records and the widely used Event Based Sampling. We apply simple machine learning techniques to determine the operating criteria. As a demonstration of capability, our method and a profiling tool are used to generate Instruction Mixes, which traditionally require good quality data at the most detailed level of granularity - basic blocks. Compared to software instrumentation, we observe an improvement in runtime of up to 76x, while keeping instruction attribution errors at 2.1% on average. In our third contribution we describe an architecture-agnostic performance analysis methodology called Hierarchical Cycle Accounting. The user is presented with a navigable hierarchy of microarchitectural issues, expressed in a metric that is universal and simple to compare - core cycles. We develop a reference implementation for the Intel Ivy Bridge microarchitecture and provide pointers for implementations on other processor architectures. Our approach and tool are successfully used by non-experts to improve and vectorize complex scientific code. Experts benefit as well - by being able to pinpoint software issues undetected by other methods, and identifying a bug in a family of Intel processors.

In distributed query processing, data shuffle is one of the most costly operations. We examined scaling limitations to data shuffle that current systems and the research literature do not solve. As the number of input and output partitions increases, naïve shuffling will result in high fan-out and fan-in. There are practical limits to fan-out, as a consequence of limits on memory buffers, network ports and I/O handles. There are practical limits to fan-in because it multiplies the communication errors due to faults in commodity clusters impeding progress. Existing solutions that limit fan-out and fan-in do so at the cost of scaling quadratically in the number of nodes in the data flow graph. This dominates the costs of shuffling large datasets. We propose a novel algorithm called Hyper Dimension Shuffle that we have introduced in production in SCOPE, Microsoft's internal big data analytics system. Hyper Dimension Shuffle is inspired by the divide and conquer concept, and utilizes a recursive partitioner with intermediate aggregations. It yields quasilinear complexity of the shuffling graph with tight guarantees on fan-out and fan-in. We demonstrate how it avoids the shuffling graph blow-up of previous algorithms to shuffle at petabyte-scale efficiently on both synthetic benchmarks and real applications.

With the growing numbers of both parallel architectures and related programming models, the benchmarking tasks become very tricky since parallel programming requires architecture-dependent compilers and languages as well as high programming expertise. More than just comparing architectures with synthetic benchmarks, benchmarking is also more and more used to design specialized systems composed of heterogeneous computing resources to optimize the performance or performance/watt ratio (e.g. embedded systems designers build System-on-Chip (SoC) out of dedicated and well-chosen components). In the High-Performance-Computing (HPC) domain, systems are designed with symmetric and scalable computing nodes built to deliver the highest performance on a wide variety of applications. However, HPC is now facing cost and power consumption issues which motivate the design of heterogeneous systems. This is one of the rationales of the European FiPS project, which proposes to develop hardware architecture and software methodology easing the design of such systems. Thus, having a fair comparison between architectures while considering an application is of growing importance. Unfortunately, porting it on all available architectures using the related programming models is impossible. To tackle this challenge, we introduced a novel methodology to evaluate and to compare parallel architectures in order to ease the work of the programmer. Based on the usage of micro benchmarks, code profiling and characterization tools, this methodology introduces a semi-automatic prediction of sequential applications performances on a set of parallel architectures. In addition, performance estimation is correlated with the cost of other criteria such as power or portability effort. Introduced for targeting vision-based embedded applications, our methodology is currently being extended to target more complex applications from HPC world. This paper extends our work with new experiments and early results on a real HPC application of DNA sequencing.

With the limitation of hardware resource and the low-efficiency of general purpose TCP/IP protocol stacks and protocol models, it is quite difficult to implement full TCP/IP protocol into embedded system when accessing to Internet. Therefore, simplified-TCP/IP stacks or UDP usually were used to substitute. A reference design of TCP/IP software architecture implementation in embedded system was proposed. Through analyzing the TCP/IP speed, code size and RAM usage in embedded system, the optimized design of clear TCP/IP interface, redundant packets-copy avoidance, realization of packets arrangement resending and window control were given. Finally, the performance and evaluation of TCP/IP software architecture in embedded system was given

Scheduling, mapping and synchronization have an essential impact on the performance of Multi-Processor System-on-Chips (MPSoCs), especially in heterogeneous systems with many cores and small tasks. This paper presents a technique to efficiently accelerate these operations. Key contribution is an Application-Specific Instruction-set Processor (ASIP) called OSIP which is especially tailored to achieve this. In contrast to pure HW solutions, OSIP is programmable and hence features higher flexibility and better scalability. OSIP comes with a compiler and a firmware that ease its usability, and an abstract formal model that allows analytical evaluation and integration into fast system level simulators. Together with OSIP, a thin software layer is proposed that leverages high level multi-task programming by abstracting OSIP's low level details away. In an extensive case study based on a synthetic benchmark and a benchmark from the multimedia domain (H.264), OSIP highlights its potential when compared against a standard RISC and an ARM926-EJS processor.

Traditional speedup models, such as Amdahls, facilitate the study of the impact of running parallel workloads on manycore systems. However, these models are typically based on software characteristics, assuming ideal hardware behaviors. As such, the applicability of these models for energy and/or performance-driven system optimization is limited by two factors. Firstly, speedup cannot be measured without instrumenting the original software codes, and secondly, the parallelization factor of an application running on specific hardware is generally unknown. In this paper, we propose a novel method, whereby standard performance counters found in modern many-core platforms can be used to derive speedup without instrumenting applications for time measurements. We postulate that speedup can be accurately estimated as a ratio of instructions per cycle for a parallel manycore system to the instructions per cycle of a single core system. By studying the application instructions and system instructions for the first time, our method leads to the determination of the parallelization factor and the optimal system configuration for energy and/or performance. The method is extensively demonstrated through experiments on three different platforms with core numbers ranging from 4 to 61, running parallel benchmark applications (including synthetic and PARSEC benchmarks) on Linux operating system. Speedup and parallelization estimations using our method and their extensive cross-validations show negligible errors (up to 8%) in these systems. Additionally, we demonstrate the effectiveness of our method to explore parallelization-aware energy-efficient system configurations for many-core systems using energy-delay-product based formulations.