FAST DIGITIZER CARD WITH INTEGRATED PEAK ANALYSIS ALGORITHM

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

Present days witnessed extensive use of Analog to Digital Converters (ADC) in different fields of applications, as an interface between the analog world and the digital world. However, in most cases, external ADCs are employed to meet the purpose. This eventually makes the system bulky, power-consuming, complex, and costly. Implementation of reconfigurable ADC programmed inside Field-Programmable Gate Array (FPGA) could reduce the system cost and power consumption substantially. Furthermore, this will make the system simple as it does not require any external circuitry for the conversion of analog input data into digital form for processing. Thus, in this paper, a multichannel reconfigurable ADC is designed, with an additional feature of time multiplexing for efficient data acquisition. The design is being implemented using 100MHz FPGA clock frequency thus can achieve a sampling rate of 100 MS/s with a resolution of 10bit for 0-2.5V signal range. The FPGA resource utilization for the complete ADC model consists of 341 FFs and 265 LUTs, with total on-chip power consumption of 14.428 W. The proposed system can also be implemented for different analog signal from transducers, depending upon the demand and requirement of sensing parameters the data collection time can be varied for transducer to transducer.

Recently, digital Intermediate Frequency (IF) waveform generators and receivers are introduced in modern radar systems to reduce the cost, size, and achieve better performance. Moreover, digital IF waveform generators achieve the requirements of high resolution and complex modulation schemes. Digital receivers have better sensitivity, wider dynamic range and lower noise Figure than analog receivers. Digital IF waveform generators and receivers work well in conjunction with a high-speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). In this paper, the design and implementation of high-speed data acquisition circuits (ADC and DAC) to generate and acquire IF waveforms are presented. Different modulated waveforms are generated digitally using Field Programmable Gate Array (FPGA). The corresponding digital receiver, including digital phase detection and matched filtering, is designed and implemented on the same FPGA chip. Design and implementation of a Printed Circuit Board (PCB) including FPGA chip and its required circuitry are introduced. The proposed design is simulated using Computer-Aided Design (CAD) tools and verified experimentally through laboratory testing.

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Development of the digital multichannel analyzer for liquid scintillation detection

Digital-sampling systems in high-resolution and wide dynamic-range energy measurements: Finite time window, baseline effects, and experimental tests

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

Compared with the four-phase optical structure, the grating encoder based on two-phase optical structure reduces the number of optical devices used in the system and makes the system more compact. Due to the high requirements for realtime and parallel processing of algorithm solution, the powerful parallel computing ability of Field Programmable Gate Array (FPGA) and customized hardware acceleration algorithm are needed to improve the real-time performance. In the previous research, the displacement signal generated by the grating encoder can be input into the FPGA through analog to digital converter (ADC) sampling, and then complete self-designed filter filtering, phase correction and displacement solution. In this paper, further, the ADC sampling rate adjustable interface is added to the FPGA, the global signal and the dc offset remove algorithm is added, and the displacement solution results in the form of fixed-point number are output to the host computer through the MicroBlaze (MB) soft core. MB core can realize process control and interface conversion on FPGA, and use a small amount of logic resources to replace the functions of MCU and DSP of traditional embedded measurement system, so as to further improve the integration of the instrument. A series of experiments are carried out on the two-phase FPGA platform. ADC sampling rate is 200ksps, 8-Channel synchronous parallel sampling, FPGA system clock frequency is 200MHz. The linear displacement table is set to drive the measurement grating at different displacement speeds, and the total stroke is set to 10mm. The FPGA real-time displacement solution platform is tested. The experimental results show that FPGA obtains accurate displacement solution results under different speed tests. In the test of 2 mm/s, the maximum cumulative displacement measurement error is 5um, which shows the real-time performance and accurate displacement solution performance of FPGA platform.

Software defined radio (SDR) is a vast and emerging field that requires the design of various technologies such as antenna, RF, IF, and digital baseband subsystems. Among all these technologies, data converters that convert signals between analog and digital domains are highly crucial. On the other hand field programmable gate arrays (FPGAs) based platforms are being preferred for evaluating and implementing the digital communication concepts due to their programmability and reconfigurability. As a result they are well suited for the design of SDR technology. In this research work, we develop a platform where high-speed data converters are interfaced with high performance FPGAs. Interfaces are designed for analog-to-digital convertors (ADC) and digital-to-analog convertors (DAC) to communicate with FPGAs. For the interface design between ADC and FPGA, a double data rate and a low voltage differential signalling based serial output is adopted. And, for the interface design between DAC and other FPGA, parallel complementary metal oxide semiconductor outputs are used. To reconfigure the modes and parameters of the data convertors, serial peripheral interface data controllers have been designed. We have through simulations evaluated the performance of our designed interfaces between data convertors and FPGAs.

With the rapid development of electronic science and technology, the signal frequency that engineers need to measure becomes higher and higher. Limited by the analog-to-digital converter (ADC) sampling rate and Nyquist sampling theorem, the digital oscilloscope can only measure waveform in a very limited range of frequency in real-time sampling mode. Therefore, it is necessary to introduce an equivalent sampling technique to increase the ability of the oscilloscope to measure higher frequency signals. In this paper, a random equivalent sampling reconstruction method based on field programmable gate array (FPGA) is proposed. In the random equivalent sampling mode, multiple sets of samples collected by the ADC are buffered in the FPGA, and the stretched circuit measures the time interval $\Delta$t between each set of trigger signals and the rising edge of the first sampling clock. Through these samples as well as the $\Delta$t in each group, the waveform can be reconstructed in FPGA, and then this reconstructed waveform can be read and displayed by the upper computer. The waveform refreshing rate of the random equivalent sampling can be greatly improved by this kind of reconstruction inside a FPGA.

The use of an automated Data Acquisition System (DAS) is very important in testing and measurement systems. The desire is extremely high in the DAS with high speed, multi-channel, and large capacity, so research in this area becomes very significant. The growing problem in DAS is to acquire the data with the required data rate and store data onto the on-chip memory. Microcontroller, microprocessor or Digital Signal Processors (DSP) devices can be programmed as a DAS, but these devices comprise problems, such as slower data acquisition rates, nonavailability of sufficient on-chip memory, etc. To overcome these above drawbacks, this paper provides an approach to design and develop DAS based on the Field Programmable Gate Array (FPGA). To acquire the data from Analog to Digital Converter (ADC) to FPGA, an Inter Integrated Circuit (I2C) serial communication protocol is used. I2C master communication protocol is designed and developed using VHDL with the Quartus II version 13.1, and the I2C master protocol is implemented in cyclone III FPGA. FPGA is acting as a master controller. DAS with the FPGA will provide the better acquisition results compared to the existing acquisition system.

The piezoelectric actuating device that consist of piezoelectric material is known for large power density with simple structure. It can generate large force than the conventional actuator and it has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with analog part and need digital to analog converters in addition to the embedded analog to digital converters, which makes the system bulky compared with the small size of the piezoelectric devices. To overcome these weaknesses, we are developing single-chip controller that can handle analog and digital signals simultaneously using mixed signal FPGA technology. We used the Smart Fusion FPGA device that integrates ARM®Cortex-M3, analog interface and FPGA fabric in a single chip and offering full customization. It gives more flexibility than traditional fixed-function microcontrollers with the excessive cost of soft processor cores on traditional FPGAs. In this paper we introduce the design of a single chip controller using mixed signal FPGA, Smart Fusion device. To demonstrate its performance, we implemented a PID controller and PWM generator in the FPGA fabric. PWM generator and PID controller showed the effective regulation of a simple 1st order plant.

The paper presents a 9-bit single slope analog to digital converter (ADC) using a two-level vernier delay line (VDL) technique. The amplitude to time conversion architecture is aim to reduce the errors due to comparator delays and input offset. Results indicated that the comparator timing error has been reduced to less than 10 ps and the offset voltage is less than 1%. The time conversion part has the maximum sampling rate of 50Msps and the time resolution of 19.5ps with the differential non-linearity (DNL) within ±0.5 LSB, and the integral non-linearity (INL) within -0.22 and 0.56 LSB. The ADC has a sampling rate of 5 Msps and is realized with the CMOS 0.18um 1P6M technology.

Fast and flexible CCD-driver system using fast DAC and FPGA

High speed data converters are required in almost all real time applications nowadays. Their high speed puts a demand on faster and reliable interfacing techniques. This paper presents interfacing of 12-bit 65-Mega Samples per Second (MSPS) Analog to Digital Converter (ADC) with Virtex-4 Xilinx Field Programmable Gate Array (FPGA). Data Clock output signal of ADC helps capturing data at both falling and rising edge of sample clock thus supporting Dual Data Rate (DDR). The Serial Peripheral Interfacing (SPI) technique is used for capturing the digitized data from ADC using Data Clock manager (DCM) block of FPGA. The digitized data is stored in First In First Out (FIFO) in FPGA and can be further processed specifically according to application like for measurement of Pulse Repetition Frequency(PRF), amplitude etc.