Fast scalable radix-4 Montgomery modular multiplier

In this paper, techniques for fast implementations of Montgomery's modular multiplication algorithm are described. These use non-redundant multi-bit recoding. These are compared regarding the area and computation requirements and compared with conventional implementation.

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), which is a type of public-key cryptography. Montgomery multiplication is commonly used as a technique for the modular multiplication and required scalability since the bit length of operands varies depending on the security levels. Also, ECC is performed in GF(P) or GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ), and unified architectures for GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) multiplier are needed. However, in previous works, changing frequency or dual-radix architecture is necessary to deal with delay-time difference between GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) circuits of the multiplier because the critical path of GF(P) circuit is longer. This paper proposes a scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ). The proposed architecture unifies 4 parallel radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> multipliers in GF(P) and a radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">64</sup> multiplier in GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute GF(P) 256-bit Montgomery multiplication in 0.23 mus.

Large integer modular multiplication and modular addition/subtraction are basic operations in elliptic curve cryptography (ECC). Traditionally, systolic array was used to implement modular multiplication. It is not efficient because of data dependency between neighbor processing elements (PEs). In this paper, we propose a compact modular multiplication and addition unit (MMAU) specific for ECC by dividing an improved Montgomery modular multiplication (MMM) algorithm into three parts, mapping them correspondingly to a 3-stage pipelined circuit and adding a small amount of hardware to the third stage of the pipeline for implementing modular addition/subtraction without affecting the performance of MMM. The MMAU computes one modular multiplication and one modular addition/subtraction in every 3(n+7) clock cycles for n-bit operands. When the pipeline is fully utilized, the MMAU can generate a result at every n+7 cycles. The experimental results show that our scheme achieves a higher throughput with less resource compared with existed ones.

Montgomery modular multiplication is widely used in public key cryptosystems. This paper presents an energy-efficient architecture for word-based Montgomery modular multiplication algorithm. Using the proposed architecture mapping scheme in dependency graph, the switching activity of kernel can be greatly reduced. In addition, the proposed design also retains one-cycle latency between neighboring processing elements. Experimental results based on TSMC 90-nm CMOS technology show that compared to the related work, the proposed design achieves about 17% reduction in energy consumption for completing one 1024-bit Montgomery modular multiplication.

Modular multiplication is an integral part of RSA cryptosystems and its performance heavily determines the performance of the encryption hardware. This paper provides a hardware implementation of Montgomery's modular multiplication algorithm using iterative architecture. The propsed design is implemented in Verilog HDL and simulated functionally using ModelSim Altera 10.1E. The synthesis is performed using Altera Quartus II 9.1 with target FPGA board Altera DE2-70. The proposed design consumes 17540 logic elements with 15480 LUT and takes 2048 clock cycles to perform multiplication process. Based on trade-off parameter AT2 measure, the proposed design offers the best performance among other designs.

Modular multiplication is considered to be the most computation-intensive operation for cryptographic algorithms involving large operands, such as RSA and Diffie–Hellman. Their key sizes have been increased significantly in recent decades to provide sufficient cryptographic strength. Thus, large integer modular multiplication algorithm with high efficiency is in demand. Montgomery modular multiplication (MMM) integrated by the spectral arithmetic can be a suitable solution. This is because MMM eliminates the time-consuming trail division, while the spectral arithmetic can speed up the integer multiplications from quadratic time to linearithmic time. This survey paper introduces the development of spectral-based MMM, as well as its two important properties: high parallelism and low complexity. Besides, different algorithms are explored to demonstrate how each of them benefits the modular multiplication. Moreover, we also compare these algorithms in terms of digit-level complexity and provide general ideas about algorithm selection when implementing modular multiplication with 1024-bit operand size and above.

In order to make the typical Montgomery's algorithm suitable for various lengths RSA, this paper proposes a scheme for an expandable RSA coprocessor. This design allows for cascading the hardware of Process Elements when larger modulo are required. The proposed design uses optimized Montgomery's modular multiplication Algorithm. The proposed architecture has distinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased.

We propose an efficient multi-exponentiation algorithm based on the modified Booth' algorithm and Montgomery's modular multiplication algorithm. The multi-exponentiation algorithm can be used to implement fast modern cryptosystems. Owing to the reduced number of multiplications, this algorithm is about 10% faster than Pekmestzi's algorithms. The proposed algorithm can be implemented in hardware as a small component. The component can then be used to form an efficient modular multi-exponentiation module by combining it with an efficient Montgomery modular multiplication module.

Modular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively.

This paper proposes a unified, scalable dual-field Montgomery multiplier architecture which can operate in both prime GF(p) and binary extension fields GF(2n) for arbitrary prime numbers and irreducible polynomials. The Montgomery multiplier architecture has advantages in speed and flexibility for operator size compared with conventional architectures using long adders or long-bit × short-bit multipliers by introducing using a balanced r-bit×r-bit dual field multiplier. Finally, the hardware size of multipliers on GF(2n) for various r, are investigated. The Montgomery multiplier provides efficient execution of Montgomery multiplication in either field for different operand lengths, which suitable be applied to elliptic curve cryptographic (ECC) processors.

Big data security is a significant concern today due to rapidly growing data volume, velocity, and varieties of data in nature. Data security is a major concern because during transmission through insecure channels. From its recognition, the Montgomery multi-digit multiplication algorithms are still well-accepted approaches in the numerical calculation, chaos arithmetic, and highperformance implementation of public key cryptosystems such as RSA, Diffie-Hellman, and the Elliptic curve cryptosystems. We have presented the comparative study of multi-digit integer multiplication algorithms, and their performance is evaluated in terms of CPU execution time. Montgomery modular multiplication is a good practice, among others.

The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

A dual-core high-performance processor for Elliptic Curve Cryptography (ECC) in GF( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> ) over Generic Weierstrass Curves was presented in this brief. Firstly, an optimized radix-128 Montgomery modular multiplication algorithm was proposed. It takes 6 clock cycles to calculate modular multiplication, which promotes the speed of elliptic curve point-addition (PA) and elliptic curve point-doubling (PD). Secondly, a dual-core hardware architecture which includes PD core and PA core to calculate elliptic curve point-multiplication (PM) was developed. It can speed up the PM by adopting parallelism with different levels and optimizing the scheduling. Finally, a data transfer architecture between PA and PD cores was proposed which requires only a 1024-bit register. It improves the speed of PM. The proposed design consumes 996k gates and compute the PM in 0.017 ms on ASIC with a 90 nm standard cell library. Moreover, the proposed design is also implemented on FPGA (Virtex-6 platform), which consumes 182k LUTs and compute the PM in 0.056 ms.

In this paper, we present Microblaze-based parallel architectures of Elliptic Curve Scalar Multiplication (ECSM) computation for embedded Elliptic Curve Cryptosystem (ECC) on Xilinx FPGA. The proposed implementations support arbitrary Elliptic Curve (EC) forms defined over large prime field ([Formula: see text]) with different security-level sizes. ECSM is performed using Montgomery Power Ladder (MPL) algorithm in Chudnovsky projective coordinates system. At the low abstraction level, Montgomery Modular Multiplication (MMM) is considered as the critical operation. It is implemented within a hardware Accelerator MMM (AccMMM) core based on the modified high radix, [Formula: see text] MMM algorithm. The efficiency of our parallel implementations is achieved by the combination of the mixed SW/HW approach with Multi Processor System on Programmable Chip (MPSoPC) design. The integration of multi MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. The Virtex-5 parallel implementations of 256-bit and 521-bis ECSM computations run at 100[Formula: see text]MHZ frequency and consume between 2,739 and 6,533 slices, 22 and 72 RAMs and between 16 and 48 DSP48E cores. For the considered security-level sizes, the delays to perform single ECSM are between 115[Formula: see text]ms and 14.72[Formula: see text]ms.

Improving the computational efficiency of modular operations for embedded systems