Fast static analysis of power grids: algorithms and implementations

Due to the rapid advances of integrated circuit technology, the size of power distribution network (power grid) is becoming larger and larger. There are usually multi-million nodes on a power grid. Analyzing these huge power grids has become very expensive in terms of both time and memory. This paper presents an efficient parallel implementation of the Additive Schwarz Method (ASM) for IR-drop analysis of large-scale power grid. Based on distributed memory system, a new data storage method is proposed to overcome memory bottleneck of traditional methods. Techniques including overlapping in multiple layer and irregular power grid, via detection and grouping are utilized to accelerate the simulation. Moreover, a new communication strategy exhibiting minimum communication overhead is proposed. The proposed method is very accurate in the final solution, with the maximum error less than 0.1mv. Experimental results on industrial medium size benchmarks show that the proposed method achieves more than 110X speedup over a state-of-the-art direct LU solver. The proposed approach can easily solve very large-scale benchmarks, while LU solver fails to obtain the solution because of system memory limitation. It is the first time reported in literature that IR-drop analysis of power grid with over 190M nodes is successfully solved within 5 minutes.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, determines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive models on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

This paper proposes a novel method for analyzing large on-chip power delivery networks via a stochastic moment matching (SMM) method. The proposed method extends the existing direct stochastic random walk method that can be only applied to DC analysis in purely resistive networks or transient analysis of RC networks with low efficiency. The new method can analyze general structure RLC networks by combining the stochastic process with frequency domain moment matching technique. As a result, we achieve better scalability than traditional frequency domain P/G analysis approaches, and better efficiency than the existing random walk transient analysis techniques. Our experimental results show that SMM can easily trade efficiency for accuracy or vise versa. SMM can easily deliver 10/spl times/-100/spl times/ speedup over a LU-based direct solver and about 10/spl times/ speedup over the pure random walk method with reasonable accuracy on large industry P/G networks.

In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is confirmed among the demonstrated in-place diagnosis and full-wave analysis.

As the size and complexity of current VLSI circuits grows, faster power grid simulation is becoming more and more desirable. In this article, we present a parallel iterative method for static VLSI power grid simulation. In the proposed enlarged-partition-based preconditioned conjugate gradient (EPPCG) power grid solver, the power grid is divided into disjoint partitions that are subsequently enlarged to obtain accurate solution within each partition. The global solution obtained by solving enlarged partition problems concurrently acts as a highly effective parallel preconditioner. The combination of effective preconditioning and efficient parallelization helps achieve very high performance. The experiments show that our parallel implementation can achieve significant speed improvement [61X--142X] over a state-of-the-art direct solver.

Electric power has become an essential part of daily life: we plug our electronic devices in, switch our lights on, and expect to have power. As the availability of power is usually taken for granted in modern societies, we mostly feel annoyed at its absence and perceive the importance of power during outages which have severe effects on the public order. Blackouts have had disastrous consequences for many countries and they continue to occur frequently. Such examples demonstrate the necessity for careful analysis and planning of power grids, to ultimately increase the reliability of power grids. The power grids have evolved due to economic, environmental and human-caused factors. In addition to the contingency analysis, nowadays, the operation and planning of power grids are facing many other challenges (such as demand growth, targeted attacks, cascading failures, and renewable energy integration). Thus, many questions arise, including: which buses (nodes) to connect with a new line (link)? What are the impacts of malicious attacks on power grids? How may an initial failure result in a cascade of failures? How to prepare for the integration of renewable energy? Answering such questions requires developing new concepts and tools for analysing and planning of power grids. Power grids are one of the largest and the most complex man-made systems on earth. The complex nature of power grids and its underlying structure make it possible to analyse power grids relying on network science. The applications of network science on power grids have shown the promising potential to capture the interdependencies between components and to understand the collective emergent behaviour of complex power grids. This thesis is motivated by the increasing need of reliable power grids and the merits of network science on the investigation of power grids. In this context, relying on network science, we model and analyse the power grid and its near-future challenges in terms of line removals/additions, malicious attacks, cascading failures, and renewable integration.

Network-on-Chip (NoC) has become the de-facto standard for on-chip communication in MPSoCs. The growing NoC power footprint, increase in the transistor current, and high switching speed of the logic devices, exacerbate the peak power supply noise (PSN) in the NoC power delivery network (PDN). Hence, preserving power supply integrity in the NoC PDN is critical. In this work, we propose PRADA (PSN-aware Runtime Adaptation)-a collection of a novel flow-control protocol (PAF) and an adaptive routing algorithm (PAR), to mitigate PSN in NoCs. Our best scheme achieves 14% and 12% improvements in the regional peak PSN and energy efficiency, with an average of 4.6% performance overhead and marginal area and power footprints.

Vectorless integrity verification is becoming increasingly critical to robust design of nanoscale power delivery networks (PDNs). To dramatically improve efficiency and capability of vectorless integrity verifications, this paper introduces a scalable multilevel integrity verification framework by leveraging a hierarchy of almost linear-sized spectral power grid sparsifiers that can well retain effective resistances between nodes, as well as a recent graph-theoretic algebraic multigrid (AMG) algorithmic framework. As a result, vectorless integrity verification solution obtained on coarse level problems can effectively help find the solution of the original problem. Extensive experimental results show that the proposed vectorless verification framework can always efficiently and accurately obtain worst-case scenarios in even very large power grid designs.

This paper presents an equivalent self-consistent electrothermal circuit model for power integrity analysis of large on-chip power distribution networks. Two coupled circuits are used to co-simulate the electrical and thermal behavior of the power grid. After a steady-state analysis, the order of the circuit is strongly reduced by means of a node clustering technique. The obtained low-order circuit allows a cost-effective complete power integrity analysis, including dynamic analysis and evaluation of time-domain features like voltage droop. As a case-study, a 45-nm chip power grid is analyzed: the full circuit for the electrothermal model with 4 million nodes is reduced by a factor of about 3500×, with a relative error on the solution below few percent.

Existing state-of-the-art realizable RC reduction methods may not be suitable for scalable power grid reductions due to the fast growing computational complexity and the large number of ports. In this work, we present a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. The first step of the proposed approach aggressively reduces the large power grid blocks into much smaller power grid blocks by properly matching the effective resistances of the original power grid networks. Next, an efficient spectral graph sparsification scheme is introduced to dramatically sparsify the relatively dense power grid blocks that are generated during the previous step. In the last, an effective grid compensation scheme is proposed to further improve the model accuracy of the reduced and sparsified power grid. Since reduction of each power grid block can be performed independently, our method can be easily accelerated on parallel computers, and therefore expected to be capable of handling large power grid designs as well as incremental designs. Extensive experimental results show that our method can scale linearly with power grid sizes and efficiently reduce industrial power grids sizes by 20X without loss of much accuracy in both DC and transient analysis.

This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-die decoupling capacitance (Cdie) and on-die resistance and on die metal grid resistance (Rdie+Rgrid) characterization. For accurate modeling of Cdie, Rdie and Rgrid, two different measurements are studied by means of ‘On-chip’ and ‘On package’ measurement. As the ‘On package’ measurement approach' is a known valid approach established and relied on for many years, it is used as a benchmark to guide us in the relatively new approach of ‘On chip’ in order to derive the right model for Cdie/Rdie/Rgrid. As both measurement setups are different, one as a direct on-chip measurement, while the other has an additional package substrate, the paper will describe a methodology to compensate the package parasitic from the model extracted; so that the final model is a standalone Cdie/Rdie/Rgrid model without the contribution of added parasitic from the package substrate. To ensure consistency, a wafer structure which consist only the power grid structure is measured and correlated with the power grid modeling tool to confirm that both modeling methodology and measurement methodology are correlated and accurate before applying the Rgrid model. The new method has shown a good correlation to the existing method to within 95% accuracy.

The biggest impact to high-performance microprocessor designs comes from the earliest design planning made up-front in the design. Of these, electrical wire planning is one of the most important. Here, designers begin by understanding the electrical impact of the width and pitch of signals and power rails as well as their inter-relationship. The features of any such pre-set global wire plan will include delay, capacitive and inductive noise, repeater instertion, electromigration, availability of wiring layers, IR drop, allowed design variability, relationship to clock distribution and several other factors. Increasingly, the relationship between each of these factors is becoming more complex and non-obvious. The power delivery network is used not only to deliver power but to shield signals and there is a tradeoff between those two requirements. Signals noise may include low probability inductive noise which is not necessarily useful. When the electrical planning is done, the result will have large implications on routability and design convergence including decap planning. Early physical wiring implication measures should ideally be included with electrical planning, but how will this be done? This talk will focus on the thinking that goes into early wire planning, including signals and power grid, which is usually subsequently fixed for the remainder of the design, and measures which may help to clarify the planning process and its impact will be suggested.

All technology options for three-dimensional integrated circuits (3D ICs) [Batude 11, Naito 10, Topol 05, Van Olmen 08, Wei 09, Wong 07] face the challenge of how to remove the heat dissipated on the upper layers (Fig. 1) [Kleiner 95]. Most existing techniques rely on an array of Through-Silicon Vias (TSVs) for this purpose. Here we report how on-chip power delivery networks (PDNs) designed to deliver noise-free power can significantly contribute to heat removal in 3D ICs.