Faster Interleaved Modular Multiplier Based on Sign Detection

The numbers of magic series of large orders are computed on Intel Xeon Phi processors with an improved and optimized Montgomery multiplication algorithm. The number of magic series can be efficiently computed by Kinnaes’ formula, of which the most time-consuming element is modular multiplication. We use Montgomery multiplication for faster modular multiplication, and the number of operations is reduced through procedural simplifications. Modular addition, subtraction, and multiplication operations are vectorized by using the following instructions: Intel Advanced Vector Extensions (AVX), Intel Advanced Vector Extensions 2 (AVX2), and Intel Advanced Vector Extensions 512 (AVX-512). The number of magic series of order 8000 is computed on multiple nodes of an Intel Xeon Phi processor with a total execution time of 1806 days. Results are compared with salient studies in the literature to confirm the efficacy of the approach.

The modular multiplication operation is the most time-consuming operation for number-theoretic cryptographic algorithms involving large integers, such as RSA and Diffie-Hellman. Implementations reveal that more than 75 percent of the time is spent in the modular multiplication function within the RSA for more than 1,024-bit moduli. There are fast multiplier architectures to minimize the delay and increase the throughput using parallelism and pipelining. However such designs are large in terms of area and low in efficiency. In this paper, we integrate the fast Fourier transform (FFT) method into the McLaughlin’s framework, and present an improved FFT-based Montgomery modular multiplication (MMM) algorithm achieving high area-time efficiency. Compared to the previous FFT-based designs, we inhibit the zero-padding operation by computing the modular multiplication steps directly using cyclic and nega-cyclic convolutions. Thus, we reduce the convolution length by half. Furthermore, supported by the number-theoretic weighted transform, the FFT algorithm is used to provide fast convolution computation. We also introduce a general method for efficient parameter selection for the proposed algorithm. Architectures with single and double butterfly structures are designed obtaining low area-latency solutions, which we implemented on Xilinx Virtex-6 FPGAs. The results show that our work offers a better area-latency efficiency compared to the state-of-the-art FFT-based MMM architectures from and above 1,024-bit operand sizes. We have obtained area-latency efficiency improvements up to 50.9 percent for 1,024-bit, 41.9 percent for 2,048-bit, 37.8 percent for 4,096-bit and 103.2 percent for 7,680-bit operands. Furthermore, the operating latency is also outperformed with high clock frequency for length-64 transform and above.

Modular exponentiation in a finite field is the basic computation involved in most public key crypto systems, such as Diffie-Hellman key exchange, ElGamal, etc. The current paper presents a new parallel architecture whereby the modular multiplication and squaring can be processed simultaneously in GF(2m) in m clock cycles using a cellular automata. Since the proposed cellular automata architecture is simple, regular, modular, cascadable, it can also be utilized efficiently for the implementation of VLSI.

Improving the computational efficiency of modular operations for embedded systems

Big data security is a significant concern today due to rapidly growing data volume, velocity, and varieties of data in nature. Data security is a major concern because during transmission through insecure channels. From its recognition, the Montgomery multi-digit multiplication algorithms are still well-accepted approaches in the numerical calculation, chaos arithmetic, and highperformance implementation of public key cryptosystems such as RSA, Diffie-Hellman, and the Elliptic curve cryptosystems. We have presented the comparative study of multi-digit integer multiplication algorithms, and their performance is evaluated in terms of CPU execution time. Montgomery modular multiplication is a good practice, among others.

Modular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively.

Modular arithmetic plays very crucial role for public key cryptosystems, such as the public key cryptosystem, the key distribution scheme, and the key exchange scheme. Modular exponentiation is a common operation used by several public-key cryptosystems, such as the RSA encryption scheme and the Diffie-Hellman key exchange scheme. In this paper, we have proposed a new method to fast evaluate modular exponentiation, which combines the complement recoding method and canonical recoding technique.KeywordsCanonical recodingmodular arithmeticcomplexity analysesfast algorithm designpublic-key cryptosystem

Modular multiplication is the fundamental operation in most public-key cryptosystem. Therefore, the efficiency of modular multiplication directly affects the efficiency of whole crypto-system. This paper presents implementation and comparison of several recently proposed, highly efficient architectures for modular multiplication on FPGAs: interleaved multiplication, two variants of Montgomery multiplication, Jeong-Burleson multiplication, multiplication based on key size partitioning and complement. Finally, new hardware architecture for time optimal modular multiplication is proposed based on Hamming weight and position of one's in multiplicand.

All public key cryptosystems, though being highly secure, have a common drawback: They require heavy computational effort. This is due to the reliance on modular multiplication of large operands (1024 bits or higher). The same problem arises in data encryption/decryption and digital signature schemes. Examples of such cryptosystems are RSA, DSA, and ECC. Now considering embedded platforms for applications of smart cards and smart tokens, the overall time performance of the cipher system becomes very slow. This refers to the limited computational power of the embedded processors. This paper introduces an enhanced architecture for computing the modular multiplication of two large numbers X and Y modulo a given modulus M. The proposed design can act as a co-processor for embedded general purpose CPUs. The proposed design is compared with three previous architectures depending on carry save adders and look up tables. Look up tables should be loaded with a set of pre-computed values. Our proposed architecture uses the same carry save addition, but replaces both look up tables and pre-computations with an enhanced version of sign detection techniques. The proposed architecture supports higher frequencies than other architectures. It also has a better overall absolute time for a single operation.

In this paper, a unified methodology is introduced for the computation of modular multiplication and reduction operations, which are fundamental to numerous public-key cryptography systems. First, a general theory is presented which aides the construction of arbitrary most-significant-digit first and least-significant-digit first iterative modular reduction methods. Utilizing this foundation, new methods are presented which are not premised in division techniques. The resultant class of algorithmic techniques, which we dub iterative residue accumulation (IRA) methods, are robust, accommodating general radixes. Furthermore, forms supporting both most-significant-digit or least-significant-digit first evaluation are presented. Significantly, in comparison to earlier methods, IRA effectively replaces quotient-digit evaluation and quotient-modulus multiplication steps encountered in techniques such as Montgomery's method with a single-step residue evaluation, thereby permitting efficiency improvements. Forms suitable for either lookup or multiplication-based evaluation are explored. Precomputation overhead is minimal and the methods are suitable for VLSI implementation.

Modular multiplication is one of the most important operations in the public key cryptographic algorithms. In order to design a high-performance modular multiplier, we present a novel hybrid Montgomery modular multiplier over GF(p) on FPGAs, which employs Karatsuba and Knuth multiplication algorithms in different levels to implement large integer multiplication. A 9-stage pipeline full-word multiplier is proposed for the 256-bit multiplication with 4-level recursion. The performance of our modular multiplier is improved through optimizing the pipeline and reducing carry-chain latency of the modular adder. On average, our modular multiplier can perform one 256-bit modular multiplication in 3 cycles. We can integrate 13 modular multipliers on a Xilinx Virtex-6 V6VSX475T FPGA. The experimental results show that the throughput of 856.9 million modular multiplications per second can be achieved and the hybrid Montgomery modular multiplier has an outstanding performance in the situations which need continuous multiplications.

Secure communication is a challenging issue in modern industries and critical infrastructures. The core technology used for securing the communication is cryptography. Modular multiplication is an important operation in cryptosystems. This paper investigates a novel modular multiplication algorithm and architecture. In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. The proposed architecture is implemented on Xilinx Virtex 5 FPGA. The complexity analysis results and FPGA implementation results show that the proposed modular multiplication algorithm and architecture provide improvement on the total computation time and area×time complexity compared to other modified modular multiplication algorithms and architectures. Keyword: Security, modular multiplication architecture, FPGA, parallel computation, compact SD

Popular public key algorithms such as RSA and Diffie-Hellman key exchange, and more advanced cryptographic schemes such as Paillier’s and Damgard-Jurik’s algorithms (with applications in private information retrieval), require efficient modular multiplication with large integers of size at least 1024 bits. Montgomery multiplication algorithm has proven successful for modular multiplication of large integers. While general purpose multi-core processors have become the mainstream on desktop as well as portable computers, utilization of their computing resources have been largely overlooked when it comes to performing computationally intensive cryptographic operations. In this work, we propose a new parallel Montgomery multiplication algorithm which exhibits up to 39 % better performance than the known best serial Montgomery multiplication variant for the bit-lengths of 2048 or larger. Furthermore, for bit-lengths of 4096 or larger, the proposed algorithm exhibits better performance by utilizing multiple cores available. It achieves speedups of up to 81 %, 3.37 times and 4.87 times for the used general-purpose microprocessors with 2, 4 and 6 cores, respectively. To our knowledge, this is the first work that shows with actual implementation results that Montgomery multiplication can be practically and scalably parallelized on general-purpose multi-core processors.

Modular exponentiation of large number is widely applied in public-key cryptosystem, also the bottleneck in the computation of public-key algorithm. Modular multiplication is the key calculation in modular exponentiation. An improved Montgomery algorithm is utilized to achieve modular multiplication and converted into systolic array to increase the running frequency. A high efficiency fast modular exponentiation structure is developed to bring the best out of the modular multiplication module and enhance the ability of defending timing attacks and power attacks. For 1024-bit key operands, the design can be run at 170MHz and finish a modular exponentiation in 4,402,374 clock cycles.

key exchange primitive is a fundamental pillar in public key cryptography. Diffie-Hellman is an example of a keyexchange protocol, which enables the establishment of shared secret key over an insecure public channel between two parties. Different instantiations of Diffie-Hellman can be found based on the underlying group/set where the computations required for establishing the shared key are carried out. In this paper, three different implementations of Diffie-Hellman protocol will be reviewed and compared: the core Diffie-Hellman (DH) protocol, Elliptic Curve Diffie-Hellman (ECDH) as examples of secure protocols in a pre-quantum world, and Supersingular Isogeny Diffie-Hellman (SIDH) as an example of a quantum-safe protocol for key establishment. The steps of establishing the shared key in each instantiation will be shown, security analysis will be discussed for the different implementations in both pre- and post-quantum world, and finally, a brief comparison of the three instantiations will be drawn.