New Parallel Architecture for Modular Multiplication and Squaring Based on Cellular Automata

Secure communication is a challenging issue in modern industries and critical infrastructures. The core technology used for securing the communication is cryptography. Modular multiplication is an important operation in cryptosystems. This paper investigates a novel modular multiplication algorithm and architecture. In the proposed algorithm and architecture, the parallel architecture and compact SD technique are utilized to improve the performance of modular multiplication operation and cryptosystems. The proposed architecture is implemented on Xilinx Virtex 5 FPGA. The complexity analysis results and FPGA implementation results show that the proposed modular multiplication algorithm and architecture provide improvement on the total computation time and area×time complexity compared to other modified modular multiplication algorithms and architectures. Keyword: Security, modular multiplication architecture, FPGA, parallel computation, compact SD

For modern cryptographic systems, the public key cryptosystem such as RSA requires modular exponentiation (M E mod N). The M, E and N are either as large as the 1024-bit integers or even larger, it is not a very good idea to directly compute M E mod N. Recently, there are many techniques have been invented to solve the time-consuming computations of such time-consuming modular exponentiation. Among these useful algorithms, the “binary (square-and-multiply) algorithm” reduces the amount of modulo multiplications. As the “signed-digit representation algorithm” has the property of the nonzero digit occurrence probability equals to 1/3, taking this advantage, this method can more effectively decrease the amount of modular multiplications. Moreover, by using the technique of recording the common parts in the folded substrings, the “folding-exponent algorithm” can improve the efficiency of the binary algorithm, thus can further decrease the computational complexity of modular exponentiation. In this paper, a new modular exponentiation algorithm is proposed which based on the binary algorithm, signed-digit representation, and the folding-exponent technique. By using the parallel processing technique, in our proposed method, the modular multiplications and modular squaring can be executed in parallel, and thus lower down the computational complexity to k + 3 multiplications. As modular squaring operation over GF(2 n ) is carried out by a simple cyclic right shift operation, the computational complexity of our proposed method can be further reduced to 29k/36 + 3 multiplications.

Modular multiplication is the fundamental operation in most public-key cryptosystem. Therefore, the efficiency of modular multiplication directly affects the efficiency of whole crypto-system. This paper presents implementation and comparison of several recently proposed, highly efficient architectures for modular multiplication on FPGAs: interleaved multiplication, two variants of Montgomery multiplication, Jeong-Burleson multiplication, multiplication based on key size partitioning and complement. Finally, new hardware architecture for time optimal modular multiplication is proposed based on Hamming weight and position of one's in multiplicand.

<p>Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now<br> directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular  ultiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.</p>

Modular exponentiation of large number is widely applied in public-key cryptosystem, also the bottleneck in the computation of public-key algorithm. Modular multiplication is the key calculation in modular exponentiation. An improved Montgomery algorithm is utilized to achieve modular multiplication and converted into systolic array to increase the running frequency. A high efficiency fast modular exponentiation structure is developed to bring the best out of the modular multiplication module and enhance the ability of defending timing attacks and power attacks. For 1024-bit key operands, the design can be run at 170MHz and finish a modular exponentiation in 4,402,374 clock cycles.

Modular arithmetic plays very crucial role for public key cryptosystems, such as the public key cryptosystem, the key distribution scheme, and the key exchange scheme. Modular exponentiation is a common operation used by several public-key cryptosystems, such as the RSA encryption scheme and the Diffie-Hellman key exchange scheme. In this paper, we have proposed a new method to fast evaluate modular exponentiation, which combines the complement recoding method and canonical recoding technique.KeywordsCanonical recodingmodular arithmeticcomplexity analysesfast algorithm designpublic-key cryptosystem

Improving the computational efficiency of modular operations for embedded systems

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), which is a type of public-key cryptography. Montgomery multiplication is commonly used as a technique for the modular multiplication and required scalability since the bit length of operands varies depending on the security levels. Also, ECC is performed in GF(P) or GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ), and unified architectures for GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) multiplier are needed. However, in previous works, changing frequency or dual-radix architecture is necessary to deal with delay-time difference between GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) circuits of the multiplier because the critical path of GF(P) circuit is longer. This paper proposes a scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ). The proposed architecture unifies 4 parallel radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> multipliers in GF(P) and a radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">64</sup> multiplier in GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute GF(P) 256-bit Montgomery multiplication in 0.23 mus.

본 논문에서는 Montgomery 알고리즘을 기반으로 시스톨릭 어레이 구조를 이용한 효율적인 Radix-4 모듈러 곱셈기 구조를 제안한다. 제안된 알고리즘을 이용하여 모듈러 곱셈을 위한 반복의 수가 감소되었으며, 따라서 n-비트의 모듈러 곱셈을 수행하기 위하여 (3/2)n+2 클럭이 소요된다. 그러나 하드웨어의 이용도를 감안할 때 두 개의 곱셈에 대한 중첩(interleaving) 연산이 가능하며, 가장 빠른 시기에 새로운 곱셈을 시작한다면 하나의 모듈러 곱셈을 수행하기 위하여 평균 n/2 클럭이 필요하다. 제안된 구조는 시스톨릭 어레이 구조의 잇점으로 규칙성과 확장성을 갖기 때문에 효율적인 VLSI 구조로 설계하기가 용이하다. 기존의 다른 구조들과 비교하여 볼 때 제안된 구조는 상대적으로 적은 하드웨어들을 사용하여 높은 수행 속도를 보여주었다. In this paper, we propose an efficient architecture for radix-4 modular multiplication in systolic array structure based on the Montgomery's algorithm. We propose a radix-4 modular multiplication algorithm to reduce the number of iterations, so that it takes (3/2)n+2 clock cycles to complete an n-bit modular multiplication. Since we can interleave two consecutive modular multiplications for 100% hardware utilization and can start the next multiplication at the earliest possible moment, it takes about only n/2 clock cycles to complete one modular multiplication in the average. The proposed architecture is quite regular and scalable due to the systolic array structure so that it fits in a VLSI implementation. Compared to conventional approaches, the proposed architecture shows shorter period to complete a modular multiplication while requiring relatively less hardware resources.

In this chapter we study the basic notions from mathematics and computer science that we will be using throughout the book. Its purpose is not to give a comprehensive account of these concepts but, rather, to study them from the point of view of their applications to cryptography, emphasizing the algorithmic aspects. For this task we will be using Maple as a tool to implement the relevant algorithms and to experiment with them. Bearing in mind these premises, we include here the required concepts and results from probability, complexity theory and modular arithmetic, including quadratic residues and modular square roots, and we also give a brief introduction to the relevant aspects of group theory and finite fields. Thus, for readers already familiar with these subjects, this chapter will hopefully serve as a refresher of the topics mentioned in the Preface (with the exception of linear algebra which is not included here) and, at the same time, as an introduction to the use of Maple to explore the algorithms discussed. Even for readers not familiar with these subjects we hope that sufficient information is included here to allow them to profitably read the rest of the book. We include proofs of most of the algorithmic and mathematical results mentioned, with pointers to the literature for the reader who wishes to go deeper on these topics and, at the same time, we will be introducing here a great deal of the notation used throughout the book.

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA’s modular exponentiation can be computed by repeated modular multiplication. Fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery algorithm, commonly used for modular multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that simplifies the operation of the Q logic in Montgomery multiplier. The resulting design was applied in modular exponentiation for lightweight applications of RSA. Synthesis results showed that the new multiplier design achieved reduce hardware area, consequently, an area-efficient modular exponentiation design. A frequency of 452.49 MHz was achieved for modular exponentiation with 85 K gates using the 130 nm technology.

Modular multiplication forms the basis of many cryptographic functions such as RSA, Diffie-Hellman key exchange, and ElGamal encryption. For large RSA moduli, combining the fast Fourier transform (FFT) with McLaughlin's Montgomery modular multiplication (MLM) has been validated to offer cost-effective implementation results. However, the conditional selections in McLaughlin's algorithm are considered to be inefficient and vulnerable to timing attacks, since extra long additions or subtractions may take place and the running time of MLM varies. In this work, we restrict the parameters of MLM by a set of new bounds and present a modified MLM algorithm involving no conditional selection. Compared to the original MLM algorithm, we inhibit extra operations caused by the conditional selections and accomplish constant running time for modular multiplications with different inputs. As a result, we improve both area-time efficiency and security against timing attacks. Based on the proposed algorithm, efficient FFT-based modular multiplication and exponentiation are derived. Exponentiation architectures with dual FFT-based multipliers are designed obtaining area-latency efficient solutions. The results show that our work offers a better efficiency compared to the state-of-the-art works from and above 2048-bit operand sizes. For single FFT-based modular multiplication, we have achieved constant running time and obtained area-latency efficiency improvements up to 24.3 percent for 1,024-bit and 35.5 percent for 4,096-bit operands, respectively.

Based on modified Booth's algorithm, a radix-4 cellular-array modular multiplier to fulfill the radix-4 modular multiplication algorithm is designed. We implement the modular multiplier in bit level and get rid of the extra control signals shown in by using the concept of guard bits. The radix-4 modular multiplier can be used to implement fast RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than the cellular-array modular multiplier based on the original Montgomery's algorithm. The time to calculate a modular exponentiation is about n/sup 2/ clock cycles, where n is the word length, and the clock cycle is roughly equal to the delay time of a full adder. The utilization of the multiplier is 100% by interleaving consecutive exponentiations.

Cellular automata (CA) have been accepted as a good evolutionary computational model for the simulation of complex physical systems. They have been used for various applications, such as parallel processing computations and number theory. In this paper, we studied the applications of cellular automata for the modular multiplications; we proposed two new architectures of multipliers based on cellular automata over finite field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). Since they have regularity, modularity and concurrency, they are suitable for VLSI implementation. The proposed architectures can be easily implemented into the hardware design of crypto-coprocessors.

key exchange primitive is a fundamental pillar in public key cryptography. Diffie-Hellman is an example of a keyexchange protocol, which enables the establishment of shared secret key over an insecure public channel between two parties. Different instantiations of Diffie-Hellman can be found based on the underlying group/set where the computations required for establishing the shared key are carried out. In this paper, three different implementations of Diffie-Hellman protocol will be reviewed and compared: the core Diffie-Hellman (DH) protocol, Elliptic Curve Diffie-Hellman (ECDH) as examples of secure protocols in a pre-quantum world, and Supersingular Isogeny Diffie-Hellman (SIDH) as an example of a quantum-safe protocol for key establishment. The steps of establishing the shared key in each instantiation will be shown, security analysis will be discussed for the different implementations in both pre- and post-quantum world, and finally, a brief comparison of the three instantiations will be drawn.