Fault Classification in Phase-Locked Loops Using Back Propagation Neural Networks

Introduction Frequency synthesizers are pervasively utilized in almost every electronic system for generation of the well-defined clock frequencies of interest. For instance, in the modern wireless transceiver, a phase-locked loop (PLL) is commonly used to generate RF frequencies to up-convert and down-convert the analog signal. On the baseband side, the mixed-signal circuit, such as switched-capacitor filters, as well as digital VLSI also require PLLs to synthesize various clock domains. Moreover, the trend of future electronic design will continue to integrate more functionality, support multiple standards, and multi-channels in a system-on-chip (SoC) platform, which will inevitably increase the number of frequency synthesizers for various analog and digital circuit blocks. As a result, minimizing the power and area consumption of a frequency synthesizer becomes increasingly critical, or it can become the dominant cost factor in the overall system. This system trend has been driving PLL design towards more reconfigurability, wider tuning range and lower cost. The digitally-assisted PLL design concept becomes a natural consequence of this trend, as the flexibility offered via digital means is always appealing. Conventionally, the frequency synthesizer is implemented using an analog approach, i.e., the charge-pump PLL, as shown in Figure 4.1(a). The basic operation of this type of PLL has been well documented in textbooks and the literature [1, 2]. In brief, it processes the phase information in the analog domain via a phase frequency detector and a charge-pump circuit, so that the phase difference turns into current pulses. This current signal is then converted into voltage form via the analog loop filter, which typically consists of capacitor and resistor array. Some degree of digitally-assisted concept was adopted for this type of PLL, mainly to digitally reconfigure the analog loop filter and voltage-controlled oscillator (VCO). For example, the PLL may be required to support different PLL loop bandwidths and/or a wide VCO tuning range. The digitally switched capacitor or resistor bank is a common choice to support this kind of operation. While this analog PLL topology has been widely adopted and proven in both the literature and commercial products, it presents a challenge to scale with technology. The analog loop filter is typically composed of bulky passive components whose values are determined by the desirable PLL loop bandwidth, and cannot be arbitrarily reduced.

Objectives: The manufactured Integrated circuits are usable only when they are free from any types of faults or error. This is even more essential in complex circuits like analog and mixed signal circuits. This paper focuses on the fault classification in the analog portion of mixed signal circuits using artificial neural networks. Methods/Statistical Analysis: All possible catastrophic possible faults in mixed signal circuits are introduced and simulated in an exhaustive manner using Cadence Simulation package. Faults are introduced one at a time and parameters were recorded. The parametric variations obtained through simulation were normalized and are used to suitably train artificial neural networks by creating them as database. The artificial neural network is trained such that it can identify correct functioning of the circuit from its faulty operation and also to further distinguish it into the component at fault, along with the type of catastrophic or hard fault. Findings: Comparative results of Feed forward neural networks trained with Levenberg-Marquardt algorithm and Radial basis function networks in the classification of faults are provided. Application/Improvements: This can be extended for the other mixed signal circuits by creating the training data using the software simulations. The hardware implementation is possible using the embedded controllers and other types of ANN can also be selected if necessary.

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

The phase locked loop (PLL) is a control system that compares the phase of the output signal with that of the input signal and proportionally varies its output based on the phase difference between them. PLL most prolifically finds its applications in frequency generation, clock and data recovery, carrier frequency generation in modulation and demodulation, frequency synthesizers, jitter and skew reduction, and many more. Mixed-signal and digital circuits employ PLL for clock generation to get the synchronous transactions with the clock. So it is mandatory to properly design the PLL to obtain minimum jitter on the clock edges. The PLL designed in this work was based on the famous charge-pump (CP) architecture and was implemented using the semiconductor laboratory (SCL) 180 nm technology in Cadence Virtuoso. This work uses NOR-based PFD using TSPC latches, Transmission gate CP, Current Starved VCO, and TSPC-based divider circuit. The proposed model of PLL has phase noise of the PLL as −113 dBc/Hz, the power consumption of the total PLL as 3.2 mW at 1.8 V power supply with deterministic jitter of about 5.62 ps and the settling time of the control voltage as 850 ns.

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed. Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL. An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit. Through integrating the D-latch with ‘OR’ logic for dual-modulus operation, the delays associated with both the ‘OR’ and D-flip-flop (DFF) operations are reduced, and the complexity of the circuit is also decreased. The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model. The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system. The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only −101.52 dBc/Hz. The circuit exhibits a low RMS jitter of 3.3 ps. The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.

The Back Propagation (BP) neural network genetic algorithm was used to identify alphabet, and the new algorithm combine the advantages of both genetic algorithm and the BP neural network. Genetic learning algorithm was used for the global optimization and BP training algorithm to accurately optimize the neural network weights and training the neural network to learn letter recognition algorithm. Add-noise alphabet of MATLAB simulation results show that the new network error recognition rate reduced by 10% compared to BP neural network and the recognition speed is also faster than the traditional BP neural network with accuracy and fast convergence.

In this paper, Lifted Wavelet Transform (LWT) and BP neural network are used for automatic flaw classification of pipeline girth welds. LWT is proposed to extract flaw feature from ultrasonic echo signals, ideally matched local characteristics of original signal and increasing the computational speed and flaw classification efficiency. After extracting features of all flaw echoes, a feature library is constructed. A modified BP neural network is followed as a classifier, trained by the library. When feature of any flaw echo is extracted and sent to BP network, flaw type is the output, realizing automatic flaw classification. Experiment results prove the proposed method, LWT with BP neural network, is more fit for automatic flaw classification than traditional methods.

Owing to verification bottleneck, analog and mixed signal IPs like Phase Locked Loop (PLL) take considerable amount of design cycle time. To evade this, we have presented detailed real value modeling approach, which facilitate analog accuracy in digital simulation, for Spread Spectrum Clock Generator (SSCG) PLL. SSCG PLLs are universally used to avoid Electro-migration Interference (EMI), major cause for silicon failure. The objective of the work is to accurately model SSCG PLL along with individual analog effects and noise behavior for full functional Mixed Signal System on Chip (MSSoC) verification. The accuracy of proposed modeling approach is validated through equivalence check with Post Layout SPICE (PLS). Such efficient models provide simulation speed-up hence, reducing Time To Market (TTM).

There is a need to develop new control strategies for interconnecting Renewable Energy Sources (RES) to the power system due to the ever increasing penetration of RES and in particular for wind power systems (WPS). The control strategies are typically based on a fast and accurate detection of the phase angle of the grid voltage which may be estimated by using a Phase-Locked Loop (PLL) control circuit. The performance of the PLL under normal and abnormal operational conditions is a crucial aspect, since the RES is desired to operate to support the power system under grid fault conditions. This paper investigates the performance of three different PLLs: a synchronous reference frame PLL (dqPLL), a stationary reference frame PLL (αβPLL), and a decoupled double synchronous reference frame PLL (ddsrfPLL). The results of this investigation motivate to the development of a new hybrid PLL which is a combination of the abovementioned PLLs and uses the advantages of each PLL. The proposed decoupled stationary reference frame PLL (dαβPLL) may be an appropriate solution to use in an interconnected RES with Ride Through Fault (RTF) capability, since it prevails the other PLLs with regards to its accuracy under unbalanced faults. Further, it has a lower deviation of the estimated phase after the fault occurs. The performance of the new hybrid dαβPLL is verified through simulations and experiments. Further the new PLL is used in an interconnected RES through experiments under normal and RTF operation.

Addressing the challenges of complex signal characteristics and difficult fault type differentiation in ultrasonic detection, a fault classification method based on Particle Swarm Optimization Support Vector Machine (PSO-SVM) is proposed. This method utilizes the particle swarm optimization algorithm to globally optimize key parameters in the support vector machine model, overcoming the limitations of traditional support vector machines, such as relying on experience for parameter selection and unstable classification performance. Taking experimental data collected from ultrasonic detection as the research object, the original signals are first subjected to feature extraction and preprocessing. Subsequently, PSO-SVM and traditional SVM models are constructed for fault pattern recognition and classification experiments, respectively. By comparing and analyzing the performance of the two methods in terms of classification accuracy and other performance indicators, the experimental results demonstrate that the PSO-optimized SVM model outperforms the standalone SVM method in both fault classification accuracy and overall recognition effectiveness. This verifies the effectiveness and feasibility of the proposed method in ultrasonic detection fault classification.

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18/spl mu/m CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

This paper presents the software implementation and analysis of phase synchronization control Techniques namely phase locked loop (PLL) and modernistic extended phase locked loop (EPLL) for controlling shunt active power filter (SAPF). The SAPF is utilized to diminish the system harmonics mostly injected by nonlinear loads. The performance of SAPF is inferior with distorted supply voltage condition, it can be improved by the phase synchronizing techniques. The PLL extract the fundamental portion from the non-sinusoidal source voltage and give input signal to the SAPF control circuit. The phase variation between the input and output signal remains constant in PLL whereas EPLL having competence to make and uphold zero phase difference between the input and output signal. The EPLL traces the magnitude and phase angle of its input signal and extracting each harmonic factor. The reference current generation for controlling SAPF uses the current extracted by these techniques. The MATLAB/Simulink model of shunt active power filter without synchronization techniques, with PLL and with EPLL technique is implemented and investigated for three phase non-linear loads. The Simulation results show that these techniques are effective and robust in the condition of distorted supply voltage for improving power quality.

A novel design for a phase-locked loop (PLL) frequency synthesizer is proposed to obtain a fast acquisition time. For conventional PLL frequency synthesizer design, the smallest frequency increment is the same as the reference frequency. Thus, a low reference frequency can only be used at the expense of a longer acquisition time. However, in the proposed PLL synthesizer, by introducing n-stage novel type cycle swallowers, the smallest frequency increment and the reference frequency can be made to be independent of each other. Therefore, by using higher feedback and reference frequencies, the proposed synthesizer can attain an acquisition performance over 10/sup 3/ times faster than that of the conventional PLL synthesizer and maintain the same smallest frequency increment for the output frequency. The performance of the design is illustrated by experimental results. >

In this paper, a triple-controlled direct digital synthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHz frequency synthesis is presented. The architecture has the merits of low spurs, a fast switching speed and high frequency resolution. It corrects the output of DDS and changes the division ratios of two variable frequency dividers in PLL to avoid high level spurs falling in the loop bandwidth of PLL. The additional DAC output is added to the output of the loop filter to drive the VCO. It provides the PLL with a fast switching speed. Experiment and measurement results showed that this type of frequency synthesizer architecture has better performance than conventional PLL and can be used in most applications of frequency synthesis.

The conventional PLL (phase locked loop) frequency synthesizer has a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are a serious problem because the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit which makes the negligible overshoot and much shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. Also, the hardware complexity and power consumption are decreased to about 28%, as compared with the conventional DH-PLL. The high speed switching characteristic in the frequency synthesis process is verified by computer simulation.