Fault Modeling and Detection for Drowsy SRAM Caches

A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using $3\times 3$ -bit local bitmap for RA only incurs about 0.08-ns delay penalty for a $512\times 16\times 32$ -bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%–11.95% increment of RR for different fault distributions.

General-purpose graphics processing units (GPGPUs) usually employ a huge register file (RF) to support massive multithreading, which however, is also responsible for a large fraction of GPGPU's total power. In this paper, we propose three RF drowsy policies and evaluate their effectiveness on leakage energy reduction. In the first drowsy policy called immediate sleep (Drowsy-IS), registers keep staying in the drowsy mode unless they are accessed, which are then put into the drowsy mode again immediately to minimize the leakage energy consumption. The second policy named temporary awake (Drowsy-TA) holds the registers in the normal (i.e. active) mode for a certain period after being accessed to wait for the next access. The registers are placed into the drowsy mode until that period expires without any access activity. Finally, we propose an adaptive policy named Drowsy-RI which identifies the re-access interval for each register at run-time and lets registers wait for the predicted intervals before putting them into the drowsy mode. The experimental results show that compared to the baseline RF, Drowsy-IS achieves 91.7% RF leakage energy reduction on average at the cost of 4.4% performance degradation. Drowsy-TA leads to negligible performance overhead, and 82.8% leakage energy reduction. By balancing the energy saving and the performance overhead, Drowsy-RI saves more RF leakage energy (87.3%) than Drowsy-TA and achieves less performance degradation (2.7%) than Drowsy-IS.

Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 × 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.

The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a real design.

In embedding RAM, built in self repair (BISR) is a successful method to improve the yeild. In this work popular march algorithm for memory testing is implemented using a BISR architecture in Modelsim. The BISR architecture is able to eliminate repeat storing of flaws in embedded RAM. Moreover,performance of the BISR for march c- and march ss are compared. This proposed technique is a cost-effective BISR strategy that only stores each defect address once. The presented BISR occupies 20% of the space and can operate at 150MHz.

With the nanometer-scale semiconductor technology, built-in self-repair (BISR) schemes are emerging techniques for improving the yield of embedded memories. A built-in self-repairable memory system typically consists of repairable memory cores, wrappers, built-in self-test (BIST) circuit, fuse group, and built-in redundancy-analyzer. This paper presents a system-level verification methodology for built-in self-repairable memory systems. The proposed verification methodology can verify the connectivity between the wrappers and self-repairable memories in a self-repairable memory system. Also, it can verify the wrapper misplaced design errors.

Using cache-like architectural components including data caches, instruction caches, or branch target buffers as a side channel, software cache-based side-channel attacks are able to derive secret keys used in cryptographic operations through legitimate software activities. Existing software solutions are typically application specific and incur substantial performance overhead. Recent hardware proposals against attacks on data caches, although effective in reducing performance overhead, may still be vulnerable to advanced attacks. Furthermore, efficient defenses against attacks on other cache structures, including instruction caches and branch target buffers, are missing. In this paper, we propose hardware-software integrated approaches to defend against software cache-based attacks comprehensively. For attacks on data caches, we propose to use preloading, informing loads, and informing loads with software random permutation to secure the partition-locked cache (PLcache), the random permutation (RPcache) and regular caches, respectively. These approaches present different tradeoffs between hardware complexity and performance overhead. To defend against attacks on instruction caches, we show that the PLcache with preloading and the RPcache provide good protection. To defend against attacks based on branch target buffers, we propose to adopt a new update policy to eliminate potential information leaking. Our experiments show that the proposed schemes not only provide strong security protection but also incur small performance overhead.

Built-in self-repair (BISR) techniques has been considered as the most cost-effective solution for enhancing yield and reliability of NAND flash memory. Owing to the inherent architecture of NAND flash memory, conventional BISR techniques use spare columns and NAND blocks as the basic replacement elements. These techniques can be categorized as the coarse-grained BISR techniques (CGBISR). It is evident that the efficiency of spare usage is very low. To cure this dilemma, fine-grained BISR (FGBISR) techniques are proposed in this paper. We first exploit the fault behaviors at the circuit level and derive novel and concise repairable fault types (RFTs) for the widely used flash memory fault models. The proposed RFTs include bit-, page-, column-, and NAND block-repairable faults. Therefore, FGBISR can conduct repairing at the fine-grained levels for improving repair efficiency. We also provide efficient redundancy analysis algorithms suitable for VLSI implementation based on the RFTs. The corresponding FGBISR architectures and repair flow are also proposed. A simulator was developed for evaluating repair rate, yield, reliability, and hardware overhead. Experimental results show that repair rate, yield, and reliability can be raised significantly with negligible hardware overhead.

In this paper, we report on a method for obtaining faults using Laser Fault Injection (LFI) in a 32-bit Microcontroller (MCU) from the Flash interface to the execution pipeline via the AHB bus. Different fault behaviors were obtained at six positions along the instruction channel. Instruction(s) were observed to be faulted with a reproducibility of 100% at each position. By collecting the faults on all the positions together and analyzing their behaviors, the faults were identified and characterized. The faults on the Flash interface buffer are different depending on the cache operation modes. When the cache is disabled, the fault is related to a block of 32 bits, whereas when the cache is enabled, the fault is related to a block of 64 bits. Two fault models, namely, replay and skip of instructions block were obtained depending on the injection position. The fault happening at the AHB bus is with a block of two instructions in both cache operation modes. Depending on the injection position, two fault models of replay and skip of two instructions were also observed. The faults on the core pipeline are related to a single instruction. The fault behavior is such that both the fetch and execution stages were faulted. The skip of a single instruction was obtained by faulting either the fetch or the execution stage of the core pipeline. By increasing the Pulse Width (PW), tens to more than one hundred of instructions were faulted at each position. The impacts of LFI parameters such as the PW and the power on the faults were studied. In addition, we compared skip fault models achieved at different positions. Our results illustrate the spatial and temporal accuracy of the LFI, thus pointing out the vulnerable positions and unveiling information of the device architecture.

Spot defects in memory devices are caused by imperfections in the fabrication process of these devices. In order to analyze the faulty effect of spot defects on the memory behavior, simulations have been performed on an electrical model of the memory in which the defects are injected, causing opens, shorts, or bridges. In this paper, simulation is used to analyze the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of most traditional memory fault models and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for eDRAMs. Conditions to test the newly established fault models, together with a test, are also given.

Previous studies have suggested using drowsy caches to reduce leakage power in caches. Such studies often move an entire cache line in and out of the drowsy mode to reduce leakage power while maintaining performance. In this work we extend previous work and introduce Application Specific Low Leakage Cache (ASL) as an alternative power-aware data cache for embedded processors. ASL builds on the observation that often only one or two words of a cache line are accessed during long periods. Accordingly, we investigate a word-size granularity approach to drowsy caches. We introduce two ASL variations, i.e., B-ASL and P-ASL. In B-ASL we move all words in a cache line into the drowsy (low leakage) mode and wakeup only the words accessed. In P-ASL we make sure recently accessed words stay in the non-drowsy (high leakage) mode to maintain performance. We show that ASL can reduce leakage power in caches by 88% while paying an average performance cost of 0.7% compared to drowsy cache..

We propose an unambiguous instruction cache software-based self-testing methodology that can generate a reliable result to precisely determine the test passed or not. We present testing cases that cause ambiguous cache testing results and propose five principles of test pattern selection to prevent these situations from occurring. To preserve the order of March sequence in testing an I-cache, we leverage cache bank and cache disable operations. In this way, we are able to implement any March algorithm without violating the sequence order. Finally, we present a case study for ARM v5 ISA processor that has an 8KB instruction cache. We use the March C- algorithm and achieve 100% of inter-word coverage and more than 97% of intra-word coverage evaluated by the RAMSES simulator.

Most schedulability analysis techniques for multi-core architectures assume a single worst-case execution time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the tasks that were executed immediately before the task under study. In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule, that takes benefit of cache reuse between pairs of consecutive tasks. We propose an exact method, using an integer linear programming formulation, as well as a heuristic method based on list scheduling. The efficiency of the techniques is demonstrated through an implementation of these cache-conscious schedules on a real multi-core hardware: a 16-core cluster of the Kalray MPPA-256, Andey generation. We point out implementation issues that arise when implementing the schedules on this particular platform. In addition, we propose strategies to adapt the schedules to the identified implementation factors. An experimental evaluation reveals that our proposed scheduling methods significantly reduce the length of schedules as compared to cache-agnostic scheduling methods. Furthermore, our experiments show that among the identified implementation factors, shared bus contention has the most impact.

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

Technology, CAD, and design are increasingly more challenged by Design-for-Manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among multiple design groups and using manual drawing techniques or semi-automated tools with different quality standards. This task becomes even more important for the RF/analog layout where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using standardized, parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, we will show that the standardized layout is the option preferred from the point of view of design, CAD, and technology.