Static and dynamic behavior of memory cell array spot defects in embedded DRAMs

Fault analysis of memory devices using defect injection and simulation is becoming increasingly important as the complexity of memory faulty behavior increases. In this paper this approach is used to study the effects of opens and shorts on the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The analysis shows the existence of previously defined memory fault models, and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for memory devices. Conditions to test the newly established fault models are also given.

Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.

This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list of faults that are likely to occur in a CMOS circuit. The realistic faults generated by FXT are used to evaluate fault models, find the realistic fault coverage of test sets, and guide future testing research. How well various fault models characterize the realistic faults can be quantitatively measured because FXT's fault list includes the relative likelihood of occurrence (weight) of each extracted fault. The value of IFA and FXT is demonstrated by the analysis of five commercial CMOS circuits. This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled. >

Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.

The steady march of Moore's Law in semiconductors has enabled the creation of ever more complex systems with electronics playing a central role. As a result, thorough testing of individual components is no longer adequate to ensure overall system performance, quality, and reliability. The rising importance of system-level test (SLT) to supplement traditional component structural test has gained wide recognition recently. To understand this trend, we examine where traditional testing falls short and where SLT fills the gap. In many cases, system failures are the result of complex component interactions leading to abnormal scenarios not attributable to simple and single root causes. Rather than being confined by traditional gate-level fault models, it might be more appropriate to develop a system-level fault model derived as an emergent property of complex systems. New definitions of fault coverage and how to automate high-coverage test generation are obvious challenges in the system domain. Recent developments in design verification which faces similar challenges in dealing with system complexity may offer possible solutions for SLT to draw on. The aim is to stimulate new ideas and directions for future research in system-based testing as upcoming 5G/IoT/AI-based applications penetrate deeper and pervasively into our daily lives.

Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: under specification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

With the introduction of the drowsy cache design technique (Kim et al., 2004), new fault behaviors appear and more restrictive design rules must be applied to the chip fabrication process. In this research, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear with the introduction of drowsy mode for memory arrays. When we derive a march algorithm for the new fault models of this low-power cache, several simplification rules are utilized to reduce the test complexity. As a result, we develop a march algorithm which can detect all SDs in either data caches or instruction caches. Since some faults occur only in drowsy mode, a built-in self-repair (BISR) scheme is developed. By utilizing BISR, the cache can still work even if some cache lines fail to work in drowsy mode

Fault tolerance in cellular automata at low fault rates

The D-A structured small-molecule-based resistive random-access memory (ReRAM) device has been well-researched in the last decade, and the switching mechanism was mainly induced by the intramolecular/intermolecular charge transfer processes from the donors to the acceptors. However, in the previous work, some small molecules with pristine electron acceptors in the backbone could still show the typical memory behaviors, of which the switching mechanism is still ambiguous. In this work, two 1,2,4,5-tetrazine based n-type small-molecular isomers, 2-DPTZ and 4-DPTZ, with the same electron acceptor, 1,2,4,5-tetrazine and pyridine, are chosen to investigate the isomeric effects on molecular packing, switching mechanism, and memory performance. Because of the abundant nitrogen atoms with a localized lone pair of electrons in the sp2 orbital, 2-DPTZ and 4-DPTZ compounds could self-assemble into a long-range ordered molecular packing through intermolecular C-H...N interactions, affording effective transporting tunnels for charge-carrier transport. As expected, the sandwich-structured ITO/2-DPTZ or 4-DPTZ/Al memory devices both showed binary memory characteristics, with 2-DPTZ based memory devices showing the write once read many times (WORM) memory behavior and 4-DPTZ based memory devices having the negative differential resistance (NDR) memory performance. These distinct ReRAM properties arose from the different morphologies of 2-DPTZ and 4-DPTZ films that were induced by the different packing styles between the adjacent molecules, as confirmed by X-ray diffraction (XRD) and tapping-mode atomic force microscopy (AFM) height images. Most importantly, the switching mechanism was thought to be attributed to the injected electrons that reduced the neutral molecules of 2-DPTZ and 4-DPTZ to their corresponding anion radicals. Thus, this present work helps us better understand the conducting mechanism of small molecules with pristine electron acceptors in the backbone and provides a supplementary guideline for designing multilevel small molecules to match the structure-stacking-property relationship.

Redox-active ferrocene-containing iridium(III) complex for non-volatile flash memory

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

Flexible multi‐colored electrochromic and volatile memory devices are fabricated from a solution‐processable electroactive aromatic polyimide with starburst triarylamine unit. The polyimide prepared by the chemical imidization was highly soluble in many organic solvents and showed useful levels of thermal stability associated with high glass‐transition temperatures. The polyimide with strong electron‐donating capability possesses static random access memory behavior and longer retention time than other 6FDA‐based polyimides. The differences of the highest‐occupied and lowest unoccupied molecular orbital levels among these polyimides with different electron‐donating moieties are investigated and the effect on the memory behavior is demonstrated. The polymer film shows reversible electrochemical oxidation and electrochromism with high contrast ratio both in the visible range and near‐infrared region, which also exhibits high coloration efficiency, low switching time, and the outstanding stability for long‐term electrochromic operation. The highly stable electrochromism and interesting volatile memory performance are promising properties for the practical flexible electronics applications in the future.

This paper addresses the efficiency of IDDQ and more specifically Delta- IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies