Robust sequential fault testing of iterative logic arrays

The author shows that, if the number of the states of the reduced flow table of an iterative logic array (ILA) is not a power of 2, then, the truth table verification of the ILA requires to test it exhaustively. Thus, in this case the theory presented by F.J.O. Dias (1976) and allowing the truth table verification of ILAs by means of C-tests, is not valid. Then the author extends this theory to the case where the ILA cells have some inputs in common (such ILAs are for instance ALUs, and the rows of multiply and divide arrays). >

Signature-based techniques are well known for the Built-in Self-test of integrated systems. We propose a novel test architecture which uses a judicious combination of mutual testing and signature testing to achieve low test area overhead, low aliasing probability and low test application time. The proposed architecture is powerful for testing highly concurrent systems in applications such as iterative logic arrays, real-time systems, systolic arrays, and low-latency pipelines which tend to have a large number of functional modules of a similar nature. The use of mutual testing helps in testing “self-loop” modules which cannot be tested using simple signature-based schemes. We provide graph-theoretic optimization algorithms to optimize the test area and test application time of the resulting test architecture.

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list of faults that are likely to occur in a CMOS circuit. The realistic faults generated by FXT are used to evaluate fault models, find the realistic fault coverage of test sets, and guide future testing research. How well various fault models characterize the realistic faults can be quantitatively measured because FXT's fault list includes the relative likelihood of occurrence (weight) of each extracted fault. The value of IFA and FXT is demonstrated by the analysis of five commercial CMOS circuits. This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled. >

This paper shows a way to define a partially-exhaustive gate transition fault model for use in catching defects that escape when using more traditional fault models. We define the gate-level transitions ATPG must create for this fault model and how this may catch un-modeled defects. Future work will analyze results of applying tests generated using this fault model against a commercial chip design.

Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.

Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.

A common observation at rifted margins is that the amount of extension measurable from faulting is too little to explain the observed crustal thinning and subsidence. This is the ‘extension discrepancy’. Several causes have been proposed, including depth‐dependent stretching (DDS) or thinning (DDT), sequential faulting, subseismic faulting and polyphase faulting. In this contribution, we explore the different possibilities, with specific reference to the west Galicia margin. If we take the observations at face value, then it seems unavoidable that the upper crust must be stretched and thinned less than the middle and lower crust, i.e. that DDS or DDT has occurred. However it is unclear where the displaced lower crust has gone as there is no inverse discrepancy. Furthermore, independent evidence against large‐scale DDT is provided by seismic velocities and by the occurrence of upper crustal, lower crustal and mantle rocks in close proximity at the deep margin. We thus reject DDT as a sole cause of the extension discrepancy, although recognize that small‐scale local DDT associated with asymmetric faulting is expected. Such small‐scale DDT is an integral part of models of sequential faulting, but these do not predict an overall extension discrepancy, so alone cannot explain one. Subseismic faulting also alone seems inadequate as it cannot explain the magnitude of the extension discrepancy observed at the deep margin. However, as subseismic faulting is a requirement of the fractal distribution of fault sizes and the limited resolution of the seismic method, it must contribute to the extension discrepancy, something that is commonly ignored. Polyphase faulting, in which the thinnest crust has been affected by more than one phase of faulting, resulting in complex and poorly imaged structural architecture, is both predicted at deep margins, and in combination with subseismic faulting, capable of explaining the extension discrepancy. We demonstrate that the west Galicia margin has undergone more than one phase of faulting, with later faults offsetting earlier ones to create complex geometries and, in combination with the expected amount of subseismic faulting, a substantial underestimate of the amount of extension.

Asymptotic delay times of sequential tests based on [formula omitted]-statistics for early and late change points

Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

This paper addresses the efficiency of IDDQ and more specifically Delta- IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies

Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature

The Groningen field is the largest onshore gas field in Europe. The gas-bearing section comprises aeolian and fluvial Rotliegend sandstones of Permian age and fluvial sandstones of Carboniferous age. Continuous production since 1963 has led to induced seismicity starting in the early 1990s.Faults at reservoir level play a major role in the seismicity in the Groningen field. Fault slip is expected when shear traction is sufficient to overcome frictional resistance on the fault surface. Clear insights into which faults and fault segments are most susceptible to seismicity could be used to optimise production and minimise the seismic risk. To gain these insights, a detailed and realistic fault model is required as input to both statistical analyses on seismicity and deterministic geomechanical modelling of seismogenic behaviour along fault planes. Geometrical seismic attributes and, subsequently, fault planes were extracted from a reprocessed and depth-imaged 3D seismic volume. This resulted in a detailed visualisation of the faults at reservoir level, with extension into the deeper strata below the reservoir in many cases. They represent fault planes with realistic dimensions and shapes. The fault map based on seismic attributes suggests the presence of faults that have not been included in studies on Groningen seismicity before. The improved fault definition correlates with recent earthquake hypocentres. We conclude that a detailed fault model of the Groningen field can be created using 3D seismic attributes and that detailed 3D fault planes can be extracted from these attributes. The results can be used as input to statistical and geomechanical analyses on seismicity.

Fault injection is a well-established technique in the research community that consists of emulating faults in order to obtain dependability-related data. Despite its potential, fault injection has been less widely adopted outside of academia, due to the expertise required to effectively conduct fault injection campaigns and to the lack of tools that can be easily adapted to different systems. This paper presents ucXception, an easy-to-install, extendable, open-source framework for orchestrating the entire lifecycle of fault injection campaigns without requiring expert knowledge and using a graphical interface. ucXception supports injection of software and hardware faults using realistic fault models and can be applied to a variety of target systems, including virtualized systems and complex cloud computing deployments. This brings fault injection to modern environments of cloud computing. As a use case, a preliminary analysis on the usage of failure models as a valid alternative to fault models is performed.

In enhanced-scan circuits, a two-pattern test < t i , t j > for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test < t i , t j > based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.

The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This paper presents a summary of research in hardware-software covalidation winch involves the verification of design correctness using simulation-based techniques. This paper focuses on the test generation process for hardware-software systems as well as the fault models and fault coverage analysis techniques which support test generation.