A Partially-Exhaustive Gate Transition Fault Model

Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.

The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list of faults that are likely to occur in a CMOS circuit. The realistic faults generated by FXT are used to evaluate fault models, find the realistic fault coverage of test sets, and guide future testing research. How well various fault models characterize the realistic faults can be quantitatively measured because FXT's fault list includes the relative likelihood of occurrence (weight) of each extracted fault. The value of IFA and FXT is demonstrated by the analysis of five commercial CMOS circuits. This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled. >

Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.

Spot defects in memory devices are caused by imperfections in the fabrication process of these devices. In order to analyze the faulty effect of spot defects on the memory behavior, simulations have been performed on an electrical model of the memory in which the defects are injected, causing opens, shorts, or bridges. In this paper, simulation is used to analyze the faulty behavior of embedded DRAM (eDRAM) devices produced by Infineon Technologies. The paper applies the new approach of fault primitives to perform this analysis. The analysis shows the existence of most traditional memory fault models and establishes new ones. The paper also investigates the concept of dynamic faulty behavior and establishes its importance for eDRAMs. Conditions to test the newly established fault models, together with a test, are also given.

The steady march of Moore's Law in semiconductors has enabled the creation of ever more complex systems with electronics playing a central role. As a result, thorough testing of individual components is no longer adequate to ensure overall system performance, quality, and reliability. The rising importance of system-level test (SLT) to supplement traditional component structural test has gained wide recognition recently. To understand this trend, we examine where traditional testing falls short and where SLT fills the gap. In many cases, system failures are the result of complex component interactions leading to abnormal scenarios not attributable to simple and single root causes. Rather than being confined by traditional gate-level fault models, it might be more appropriate to develop a system-level fault model derived as an emergent property of complex systems. New definitions of fault coverage and how to automate high-coverage test generation are obvious challenges in the system domain. Recent developments in design verification which faces similar challenges in dealing with system complexity may offer possible solutions for SLT to draw on. The aim is to stimulate new ideas and directions for future research in system-based testing as upcoming 5G/IoT/AI-based applications penetrate deeper and pervasively into our daily lives.

Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.

Fault tolerance in cellular automata at low fault rates

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

Advanced chips, built on innovative process nodes, are more susceptible to defects during manufacturing, making early detection critical. This necessity has driven the demand for extensive structural scan testing to screen for defects in the digital logic of System-on-Chips. The widely adopted Stuck-At (SA) and Transition-Delay (TD) scan ATPG fault models are not sufficient for screening out the defective parts and achieving low DPPM automotive parts. Targeted pattern generation for the SA and TD fault models is done only using port-level faults. Hence, the cell internal defects are not always visible via SA and TD patterns. The more recently developed Cell-Aware (CA) fault model has been successfully proven to be able to screen out the cell-internal defects. However, this approach incurs significant overhead, including CA-UDFM (user-defined fault model) generation. In this work, we present CTFM (CMOS Transition Fault Model), which uses custom UDFM files that target cell internal faults at the transistor level with less overhead compared with CA patterns. This is crucial for legacy designs, where fewer resources are typically allocated, especially compared to New Product Introduction (NPI) designs. A custom in-house diagnosis flow using our UDFM to improve scan diagnosis quality is also presented in this work.

A study is presented concerning the efficiency of test pattern sets generated with the transition fault model applied to fine grained delay fault models. The authors have developed the delay fault simulator DELFI-a program which is capable of simulating timing failures of combinational circuits using different delay fault models. For the computer experiments the authors selected transition fault test pattern sets because they are very cost-effective to generate. The simulations of benchmark circuits demonstrate that the transition fault test patterns detect gross delay faults even at nodes with redundant stuck-at faults. Furthermore the results show that the transition fault test patterns are not sufficient for small delay faults in the range of a few gate delays. In order to receive a satisfactory coverage for these delay faults, the transition fault test sets must be extended. >

In this paper, we study fault tolerance measures for m-ary n-dimensional hypercubes based on the concept of forbidden faulty sets. In a forbidden faulty set, certain nodes cannot be faulty at the same time and this model can better reflect fault patterns in a real system than the existing ones. Specifically, we study the bounds of the minimum vertex cut set for m-ary n-dimensional hypercubes by requiring each node to have at least k healthy neighbors. Our result enhances and generalizes a result by Latifi et al. for binary hypercubes. Our study also shows that the corresponding result based on the traditional fault model (where k is zero) tends to underestimate network resilience of large networks such as m-ary n-dimensional hypercubes.

Long-period seismic sources associated with glacier motion have been recently discovered, and an increase in ice flow over the past decade has been suggested on the basis of secular changes in such measurements. Their significance, however, remains uncertain, as a relationship to ice flow has not been confirmed by direct observation. Here we combine long-period surface-wave observations with simultaneous Global Positioning System measurements of ice displacement to study the tidally modulated stick-slip motion of the Whillans Ice Stream in West Antarctica. The seismic origin time corresponds to slip nucleation at a region of the bed of the Whillans Ice Stream that is likely stronger than in surrounding regions and, thus, acts like an 'asperity' in traditional fault models. In addition to the initial pulse, two seismic arrivals occurring 10-23 minutes later represent stopping phases as the slip terminates at the ice stream edge and the grounding line. Seismic amplitude and average rupture velocity are correlated with tidal amplitude for the different slip events during the spring-to-neap tidal cycle. Although the total seismic moment calculated from ice rigidity, slip displacement, and rupture area is equivalent to an earthquake of moment magnitude seven (M(w) 7), seismic amplitudes are modest (M(s) 3.6-4.2), owing to the source duration of 20-30 minutes. Seismic radiation from ice movement is proportional to the derivative of the moment rate function at periods of 25-100 seconds and very long-period radiation is not detected, owing to the source geometry. Long-period seismic waves are thus useful for detecting and studying sudden ice movements but are insensitive to the total amount of slip.

Summary form only given: Embedded memories have become the fastest growing segment of Systems on Chip (SoC) in recent years. According to the International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing SoC chip area in the future, approaching 94% within one decade. Hence, these memories will severely impact all aspects of SoC manufacturing including yield, quality and reliability. Additionally, nanotechnology is causing higher levels of device-parameter variations and new failure mechanisms that are not yet well understood. Precise fault modeling to design efficient tests is therefore essential in order to keep the test cost and test time within economically acceptable limits, while keeping higher product quality. The objective of this embedded tutorial is to provide test engineers, memory and ASIC designers, researchers, students and managers with an overview of state-of-the art of fault models for SRAMs (including traditional fault modeling and recent development in fault models for current and future technologies), together with the latest test algorithms. Next, it describes test plans, which are shown to depend on the size of the SRAM, its speed, and the application domain. Thereafter, industrial results are used to show the effectiveness of the proposed algorithms and stresses. Last, future challenges in embedded memory testing (e.g., in fault modeling, test design) are highlighted.

This paper addresses the efficiency of IDDQ and more specifically Delta- IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies

The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: functional clock at-speed, functional clock static-based and functional clock delay. The introduced models are based on the primary input values, on the primary output values and on the state bits values of the programming prototype. The presented experimental results explore the possibilities of the functional test that is constructed on the base of the static-based fault model to detect the transition and stuck-at faults. The fault coverage of the functional static-based, stuck-at and transition faults corresponds with one another quite well.