Hardware-software covalidation: fault models and test generation

Hardware/software systems are embedded in devices used to enable all manner of tasks in society today. The increasing use of hardware/software systems in cost-critical and life-critical applications has led to the heightened significance of design correctness of these systems. A summary is presented of research in hardware/software covalidation. The general covalidation problem involves the verification of design correctness using simulation-based techniques. The focus is on the test generation process, the fault models and fault coverage analysis techniques, and the test response analysis techniques employed in covalidation. The current state of research in the field is summarised and future areas for research are identified.

This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.KeywordsBoolean FunctionLogic ModuleTest GenerationField Programmable Gate ArrayFunction IdentificationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

As semiconductor content penetrates deeper into our everyday lives, the quality of the electronic components that surrounds us becomes ever more important, particularly for those involved in safety-critical applications such as automated vehicles and healthcare. For integrated circuits (IC), cell-aware testing (CAT) is the latest advancement in the drive towards zero end-user defects. CAT targets physical defects such as bridges and opens at the transistor level inside standard logic cells used to construct the IC. A fairly onerous process involving extensive analog simulation is used to characterize cell behavior in the presence of defects, and create fault models to guide the generation of chip-level test patterns that can detect these physical defects. Assuming use of a single analog simulator license, cell-aware fault modeling (CAFM) for a library of standard cells can take up to weeks to months of computation. Moreover, for certain types of defects, stand-alone library-based CAFM fails to account for strong interactions with the cell's surrounding design context on an instance basis. As a result, the created fault model may fall short in generating the optimal chip-level test patterns for defect detection and accurate failure diagnosis. In this talk, we propose the idea of "in-situ" CAFM to properly account for cell instance design context. To realize in-situ CAFM in practice, drastic improvements in efficiency and performance of the characterization process is needed. We show how a transistor switch-based approach involving switch-level fault proxies and test generation can achieve the required performance gain by eliminating much unnecessary analog simulation. Early experimental data demonstrates CAFM can be improved by two orders-of-magnitude using our approach.

Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

We define the concepts of z-sets and z-detections for combinational circuits (or the combinational logic of scan circuits). Based on these concepts we define structural characteristics and characteristics based on fault simulation. We show that these characteristics determine the numbers of fault pairs that are guaranteed to be distinguished by a given fault detection test set. These fault pairs do not need to be considered during diagnostic fault simulation or test generation. We demonstrate that benchmark circuits as well as industrial circuits have these characteristics to a larger extent than may be expected. As a result, only small percentages of fault pairs need to be considered during diagnostic fault simulation or test generation once a fault detection test set is available. In addition, these fault pairs can be identified efficiently.

The increasing use of large and very large scale integration (LSI and VLSI) have introduced many difficulties in testing large logic networks. This generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks, with and without fan-in, fan-out constraints, were described in previous papers. Procedures for efficient fault simulation and test generation will be presented here. First, a basic cell model will be introduced. Next, procedures for generating a complete fault detection set for the complex cell will be given. Both minimal and near-minimal solutions will be presented for both fan-out free and arbitrary cells respectively. The efficiency of this technique will be compared with conventional testing techniques (e.g. N-dimensional path sensitization automatic test generator with a parallel fault simulator) and the results will be reported. Finally, some future work problems will be introduced and the application of this technique for improving LSI and VLSI testability will be discussed.

The paper presents a novel approach to high-level fault modeling and test generation for microprocessors using High-Level Decision Diagrams (HLDD). A general frame-work and novel techniques for automated software-based self-test program generation are discussed. On this basis new previously not published test quality improvement capabilities of the approach are high-lighted and explained. Based on the high level fault model defined for HLDDs a novel class of hard-to-test faults, called unintended actions, is proposed. In addition, the mechanisms for reducing the risk of fault masking is explained. The experimental results show the superiority of the new method by achieving a higher quality of tests with shorter length compared to the previous results.

A method for generating tests for gate-level stuck-at faults in sequential machines is given, which is applicable when a state-table description of the machine under test is either given or extractable from the given description. A test generation procedure for faults in the state table is first described. The test generation procedure is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given state-table fault, the procedure provides either a minimum-length test, or a proof that the fault is undetectable. This test generation procedure is used for generating complete test sets for stuck-at faults in a gate level implementation of the machine, by translating stuck-at faults in the gate-level implementation into faults in the state table. The translation includes modeling and extraction. Modeling consists of a simple method to select a small subset of state-table faults such that a test set for these faults yields very high coverage of stuck-at faults in the actual implementation. Extraction consists of accurate translation of stuck-at faults in the implementation into equivalent state-table faults, and can be used to derive tests for stuck-at faults which are not detected by the test set for the modeled faults. Based on the test generation algorithm developed and the modeling and extraction of stuck-at faults to translate them into state-table faults, a method to achieve 100% fault-efficiency for stuck-at faults is proposed, and experimental results for stuck-at faults are presented. Short test sequences are shown to be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

SAT-based generation of compressed skewed-load tests for transition delay faults

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient test generation is crucial for the simulation-based verification. We present an efficient test generation methodology using SAT-based bounded model checking (BMC). This paper addresses two important challenges in test generation using SAT-based BMC: determination of bound for each property, and application of design and property decompositions to improve test generation time as well as memory requirement. Our experimental results using a MIPS processor demonstrate the feasibility and usefulness of our approach.

In enhanced-scan circuits, a two-pattern test &lt; t i , t j &gt; for a transition fault can be obtained by using a test t j that detects a stuck-at fault, and preceding it by a test t i that activates another stuck-at fault. Thus, test generation for transition faults can be done by combining pairs of stuck-at tests. This provides an alternative to deterministic test generation, as well as reduces the test storage requirements for transition fault tests. We study the possibility of generating scan-based tests for transition faults in standard-scan circuits in a similar way, by combining pairs of stuck-at tests. Since it is not always possible to obtain a standard-scan test that is equivalent to a two-pattern test &lt; t i , t j &gt; based on stuck-at tests t i and t j , it is not always possible to guarantee that the combination of t i and t j will detect a transition fault. To compensate for this, it is necessary to try combinations of different stuck-at test pairs, resulting in an increased simulation effort to compute effective standard-scan tests. Our focus in this work is on reducing this simulation effort by reducing the number of stuck-at test pairs that need to be considered.