New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

The paper describes, first, a technique to automatically generate extended finite state machines (EFSMs) and high-level decision diagrams (HLDDs) from HDL descriptions. Then, these two paradigms are exploited inside a functional test pattern generator. The goal is to combine the beneficial properties of the above paradigms using EFSMs for targeting control FSM transitions and variable-oriented HLDDs for targeting bit-coverage faults in the data variables, respectively. Experimental results show that combining the two computational models in a functional ATPG yields indeed in higher fault coverage.

The proliferation of system-on-chip designs is forcing us to consider the possibility of doing all design phases at the highest possible levels of abstraction. Behavioral-level design tools are today commercially available, and offer a solution to this problem. Conversely, test issues are usually addressed at the lowest levels of abstraction and, although in recent years many efforts have been devoted to the definition of strategies for addressing test at the high level, a global solution is yet to come. We present preliminary experimental results about some of the available high-level fault models working at the register-transfer (RT) level. The experimental procedure we adopted is presented and some preliminary results are discussed.

Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

The use of model checking to validate descriptions of digital systems lacks a coverage metrics. If the set of formal properties defined to prove the correctness of the design is incomplete, the verification can lead to a false sense of security. This paper refines, extends, and compares with other symbolic approaches, a methodology to estimate the incompleteness of formal properties, which exploits a high-level fault model and functional ATPG.

The increasing use of hardware-software systems in cost-critical and life-critical applications has led to heightened significance of design correctness of these systems. This paper presents a summary of research in hardware-software covalidation winch involves the verification of design correctness using simulation-based techniques. This paper focuses on the test generation process for hardware-software systems as well as the fault models and fault coverage analysis techniques which support test generation.

This paper derives a fault model for one-time programmable FPGAs from the general functional fault model and an algorithm to perform test generation according to this model. The new model is characterized by the abstraction of functional faults from a set of possible implementations of a circuit. In contrast to other functional-level test generation procedures a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.KeywordsBoolean FunctionLogic ModuleTest GenerationField Programmable Gate ArrayFunction IdentificationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones.KeywordsEvolutionary AlgorithmClock CycleFault ModelFault CoverageFault SimulationThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

High reliability is an important requirement for all electronic integrated circuits including superconductive systems. Reliability and yield can be categorized by the failure paths, sequence of faults due to a physical failure, and failure mechanism. Determining the defects and faults is essential to enhance the lifetime of superconductive systems. Josephson junctions (JJs) are the base element of single flux quantum systems. The primary contributions described in this paper are a set of JJ-based fault models followed by a methodology for developing high level fault models. Based on these models, test vectors can be generated to detect the type and/or location of these JJ faults.

Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

As semiconductor content penetrates deeper into our everyday lives, the quality of the electronic components that surrounds us becomes ever more important, particularly for those involved in safety-critical applications such as automated vehicles and healthcare. For integrated circuits (IC), cell-aware testing (CAT) is the latest advancement in the drive towards zero end-user defects. CAT targets physical defects such as bridges and opens at the transistor level inside standard logic cells used to construct the IC. A fairly onerous process involving extensive analog simulation is used to characterize cell behavior in the presence of defects, and create fault models to guide the generation of chip-level test patterns that can detect these physical defects. Assuming use of a single analog simulator license, cell-aware fault modeling (CAFM) for a library of standard cells can take up to weeks to months of computation. Moreover, for certain types of defects, stand-alone library-based CAFM fails to account for strong interactions with the cell's surrounding design context on an instance basis. As a result, the created fault model may fall short in generating the optimal chip-level test patterns for defect detection and accurate failure diagnosis. In this talk, we propose the idea of "in-situ" CAFM to properly account for cell instance design context. To realize in-situ CAFM in practice, drastic improvements in efficiency and performance of the characterization process is needed. We show how a transistor switch-based approach involving switch-level fault proxies and test generation can achieve the required performance gain by eliminating much unnecessary analog simulation. Early experimental data demonstrates CAFM can be improved by two orders-of-magnitude using our approach.

A mechanism is presented to represent failures in complex combinational digital and VLSI designs at a high level, referred to as behavior fault models. The advantages of behavior fault modeling include early estimates of reliability of the design in the design process, reduced CPU time for fault simulation, and results that may be more comprehensive to the high-level architects. Digital and VLSI components are expressed in a high-level hardware description language and the fault models proposed are based on the failure modes of the language constructs of a generic hardware-description language. Evaluation of such fault models is also reported through a correlation of the behavior fault simulation results of representative example designs with fault simulation of equivalent gate-level representations in the presence of stuck-at faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Reversible logic has been proposed as one solution to the problem of ever increasing power consumption. Work in areas such as synthesis techniques in reversible logic is growing, as is work on testing approaches. Numerous fault models have been proposed, but many researchers are still utilising models proposed for traditional logic. We provide an overview of the various fault models and testing approaches for reversible logic, as well as highlighting important results and comparisons/connections between the various models.