On behavior fault modeling for combinational digital designs

IntroductionThe conventional method for teaching removable partial denture (RPD) design using a pencil drawing on a solid cast has always been the basis for teaching RPD design in most dental schools at both the undergraduate and graduate levels. This does not apply to RPD fabrication technology, as more laboratories have recently adopted more efficient and versatile digital techniques to design and fabricate RPD frameworks.MethodsAt the University of Iowa College of Dentistry, we created a pilot workshop to assess the efficiency of a new approach to teaching RPD design utilizing this new digital RPD technology as a teaching tool for graduate prosthodontics residents. Three first-year prosthodontics residents were enrolled in the workshop, which involved learning the new digital workflow of designing RPD.ResultsThis new teaching approach very successfully achieved its educational goals. The residents reported that the digital RPD teaching approach enriched their knowledge and deepened their understanding of RPD design.DiscussionThe technique garnered significant interest from the students and seemed to also increase their understanding of the steps involved in RPD fabrication as well as the different components of the RPD.

Electronic systems are essential parts in the everyday life, and these systems have grown continuously in their performance and in their complexity. Therefore, the design process for such a system has also become more and more complex and has become a critical challenge. A popular tool for solving the design process of complex systems is SystemC. SystemC is a C++ language class library, which allows the modeling of hardware behavior in a programming language for software. Advantages by the usage of SystemC are e.g. an integrative concept of the design description in a continuous design flow, combined with a fast execution of compiled code during the simulation process. This chapter describes the simulation of faults in electronic systems by the usage of SystemC. It treats especially faults in hardware, which can occur after a successful validation of the design. The simulation of faults is well known in two operation areas. One field is the fault simulation of test pattern for the detection of fabrication faults. The other field is the simulated fault injection that the effects of faults emerging during the operation of the device. Such procedures are important for analysis of electronic system designs for safety critical applications with respect to their dependability under fault conditions. At first, the chapter explains some issues in the context of fault injection and fault simulation. Furthermore, it relates something about SystemC and the possibility to simulate the design. State of the art applications are also presented for this purpose. A prerequisite for a simulation is an appropriate modeling. The modeling of faults is presented in the context of their design level. It is also shown how a simulation with fault models can be implemented by several injection techniques. In addition, the advantages and disadvantages of the injection techniques are explained. Another challenge for a simulation task is the execution in an acceptable amount of time. Approaches are presented, which help to speed up simulations. Some practical simulation environments are shown at the end of the chapter.

The authors describe a method for performing transistor-level logical fault simulation. The method relies on switch-level modeling and uses a switch-level matrix-equation formulation and solution into which fault models are inserted in a straightforward manner. The fault models include transistor stuck-at, node stuck-at, and bridging faults. Both output voltage monitoring and current testing are used for fault detection. The approach has been implemented in a concurrent fault simulator and tested using both combinational and sequential circuit benchmarks. The results of the simulator compare very favourably with existing switch-level fault simulators while allowing more complete transistor-level fault models to be included. >

Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Supply current test is well established for digital CMOS circuits and the advantages of improved observability and reliability indication have prompted its use for analogue and mixed signal circuits. A short review of the literature on this subject is given. Fault simulation is used for the investigation of dynamic supply current test of a PLL, confirming existing results from smaller circuits that a combination of supply current and output voltage monitoring leads to higher fault coverage. In the paper, fault coverage is further improved, using crosscorrelation of the supply current and output signals, and the potential for BIST implementation of this technique is demonstrated using low resolution polarised crosscorrelation. Fault simulation is also performed on an analogue multiplier to investigate the effect of process parameter deviations on the supply current. The fault coverage is found to be improved by removing the DC component of the signal. Encouraging results are obtained from the application of supply current test techniques to a commercial mixed signal ASIC currently beyond the capabilities of analogue fault simulation, indicating that efforts at improving fault simulation in this area are worthwhile. The requirements for fault modelling and simulation to support supply current test are discussed and some initial results of accelerating this process using macromodelling are presented.

Self-healing reconfigurable logic using autonomous group testing

A CNN-based algorithm, adequate for short exposure image processing and an application-specific computing architecture developed to accelerate its execution are presented. Algorithm is based on a flexible and scalable CNN architecture specifically designed to optimize the projection of CNN kernels on a programmable circuit. The objective of the proposed algorithm is to minimize the adverse effect that atmospheric disturbance has on the images obtained by terrestrial telescopes. Algorithm main features are that it can be adapted to the detection of several astronomical objects and it supports multi-stellar images. The implementation platform made use of a High Performance Reconfigurable Computer (HPRC) combining general purpose standard microprocessors with custom hardware accelerators based on FPGAs, to speed up execution time. The hardware synthesis of the CNN model has been carried out using high level hardware description languages, instead of traditional Hardware Description Languages (HDL).

This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

In the first part of the chapter, an introduction to the problem of logic level fault simulation is given together with the overview of existing fault simulation techniques. The remaining part of the chapter describes a new approach to fault simulation based on exact critical path tracing to conduct fault analysis in logic circuits. A circuit topology driven computational model is presented which allows not only to cope with complex structures of nested reconvergent fan-outs but also to carry out the fault reasoning for many test patterns concurrently. To achieve the speed-up of backtracing, the circuit is simulated on higher than traditional gate level. As components of the circuit network, fan-out free regions of maximum size are considered, and they are represented by structurally synthesized BDDs. The latter allow to reduce the number of internal variables in the computation model, and therefore to process the whole circuit faster than on the flat gate-level. The method is explained first, for the stuck-at fault model, and then generalized for an extended class of functional fault model covering the conditional stuck-at and transition faults. The method can be used for simulating permanent faults in combinational circuits, and transient or intermittent faults both in combinational and sequential circuits with the goal of selecting malicious faults for injecting into fault tolerant systems to evaluate their dependability. Experimental results are included to give an idea how efficiently the method works with different fault classes.

This work proposes the modeling and simulation of short-circuit faults in inverter-based microgrids using steady-state equivalent models. A grid-forming inverter is modeled as a voltage source with equivalent positive- and negative-sequence impedances, while a grid-following inverter is represented with a current source injecting constant power. Both equivalent circuit models are developed based on voltage and current control loops and current limiters of detailed models designed for time-domain simulation. The accuracy of the proposed models is validated by comparing short-circuit voltages and currents computed using OpenDSS to those obtained from time-domain simulation using PSCAD/EMTDC. Simulation results showed that the steady-state equivalent circuit models precisely reproduce the response of the detailed models and improve computational efficiency.

This paper presents the issue of dynamic multi-level simulation of hardware designs that addresses the problem of inefficiency associated with the conventional static multi-level simulation ap proaches as in ADLIB-SABLE (Hill 1980), DIANA (Demou and Arnout 1979), and SPLICE (Newton 1978). In this approach, digital sim ulation or verification (McWilliams 1980) of hardware designs is initiated at a high level of abstraction. When detailed results are required for one or more high-level components or for tracing the source of an error to any of the lower-level devices, the appropriate components are expanded into their lower-level implementations. Then simulation or verification initiates at that level. Following completion of execution at the lower level, con trol returns to the higher level. Consequently, only those sub parts of a digital design are selected for expansion and detailed simulation that are dynamically warranted by the higher-level simulation results. Unnecessary simulation effort may be elimi nated. Dynamic multi-level simulation or zooming is a generaliza tion of the swapping technique (Szygenda 1973) to functional and fault simulation and timing verification and to the differ ent abstraction levels in the hierarchy between the gate- and behavior-levels. This paper also addresses the implementation of zooming in the rule-based design verifier, RDV (Ghosh 1984), at Stanford University. That RDV uses Ada (U.S. Dept. of Defense 1983) as a hardware description language and simulation envi ronment (Ghosh 1985).

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.

A process is presented to validate fault models used in fault diagnosis. Known defects are inserted, using a focused ion beam (FIB), into production ICs and their behavior is compared to that predicted in fault simulation. The fault model is refined until it matches the observed defect behavior. The process is then repeated with known defects in unknown (blind) locations, and necessary modifications to the model are again made. Finally, the model is used to diagnose chips with unknown defects. Experimental results on several chips demonstrate the value of the approach, which can be extended to test pattern generation and test quality estimation as well as fault diagnosis.

There is a very strong requirement for high level mixed-signal simulation in the design of complex mixed-signal ASICs, for design verification, design analysis and system level modelling. The key issues in such simulations are high level analogue modelling, and compatibility between analogue and digital simulation. The two main alternative approaches are to link together a circuit simulator and a logic simulator, providing some method of high level analogue modelling in the circuit simulator, or to develop high level event-driven models of analogue functions in the context of a digital simulator. There are advantages and disadvantages to each approach.